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description the 7542 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 7542 group has serial interfaces, 8-bit timers, 16-bit timers, and an a/d converter, and is useful for control of home electric ap- pliances and office automation equipment. features basic machine-language instructions ...................................... 71 the minimum instruction execution time ............................. 0.25 s (at 8 mhz oscillation frequency, double-speed mode for the shortest instruction) memory size flash memory version: rom ..................... 16 to 32k + 4k bytes ram ..................................... 1024 bytes mask rom version: rom ............................. 8k to 16k bytes ram ............................ 384 to 512 bytes rss version ram ..................................... 1024 bytes programmable i/o ports 29 (25 in 32-pin version and pwqn0036ka-a package version) interrupts ................................................. 18 sources, 16 vectors t imers ............................................................................. 8-bit ? 2 ...................................................................................... 16-bit ? 2 output compare ............................................................ 4-channel input capture ................................................................ 2-channel serial interface ............ 8-bit ? 2 (uart or clock-synchronized) a/d converter ............................................... 10-bit ? 8 channels (6 channels in 32-pin version and pwqn0036ka-a package version) clock generating circuit ............................................. built-in type (low-power dissipation by an on-chip oscillator) (connected to external ceramic resonator or quartz-crystal oscillator permitting rc oscillation) w atchdog timer ............................................................ 16-bit ? 1 power source voltage x in oscillation frequency at ceramic oscillation, in double-speed mode at 8 mhz .................................................................... 4.5 to 5.5 v x in oscillation frequency at ceramic oscillation, in high-speed mode at 8 mhz .................................................................... 4.0 to 5.5 v at 4 mhz .................................................................... 2.4 to 5.5 v at 2 mhz .................................................................... 2.2 to 5.5 v x in oscillation frequency at rc oscillation in high-speed mode or middle-speed mode at 4 mhz .................................................................... 4.0 to 5.5 v at 2 mhz .................................................................... 2.4 to 5.5 v at 1 mhz .................................................................... 2.2 to 5.5 v power dissipation ................................................ 27.5 mw (typ.) operating temperature range ................................... ?0 to 85 ? application office automation equipment, factory automation equipment, home electric appliances, consumer electronics, etc. rev.3.03 jul 11, 2008 page 1 of 117 rej03b0006-0303 7542 group single-chip 8-bit cmos microcomputer rej03b0006-0303 rev.3.03 jul 11, 2008
7542 group rev.3.03 jul 11, 2008 page 2 of 117 rej03b0006-0303 fig. 2 pin configuration (package type: prsp0036ga-a) pin configuration (top view) fig. 1 pin configuration (package type: plqp0032gb-a) outline plqp0032gb-a (32p6u-a) p0 7 (led 07 )/s rdy2 p1 0 /r x d 1 /cap 0 p1 1 /t x d 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 / an 0 p2 1 / an 1 32 31 30 29 28 27 26 25 p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 p3 0 (led 10 )/cap 1 v ss x out x in 9 10 11 12 13 14 15 16 8 7 6 5 3 14 v cc cnv ss reset p2 2 /an 2 p0 5 (led 05 )/txd 2 20 17 18 19 21 24 p0 2 (led 02 )/cmp 1 p0 4 (led 04 )/rxd 2 p0 3 (led 03 )/tx out p0 6 (led 06 )/s clk2 23 22 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 m37542mx-xxxgp m37542fxgp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref 2 packa g e t yp e: prsp0036ga-a ( 36p2r-a ) 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 cnv ss x out x in v ss p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 vcc v ref p0 5 (led 05 )/txd 2 p1 0 /r x d 1 /cap 0 p2 6 /an 6 p2 7 /an 7 p1 1 /t x d 1 p1 2 /s clk1 p1 3 /s rdy1 p2 3 /an 3 p2 2 /an 2 p2 1 /an 1 p2 0 /an 0 p3 1 (led 11 )/cmp 2 p3 6 (led 16 )/int 1 p2 4 /an 4 p2 5 /an 5 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 reset m37542mx-xxxfp m37542fxfp p1 4 /cntr 0 p3 5 (led 15 ) p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 7 (led 17 )/int 0 p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out
7542 group rev.3.03 jul 11, 2008 page 3 of 117 rej03b0006-0303 fig. 4 pin configuration (package type: pwqn0036ka-a) fig. 3 pin configuration (package type: prdp0032ba-a) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnv ss p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 v cc x in x out v ss p1 1 /t x d 1 p1 0 /r x d 1 /cap 0 p0 7 (led 07 )/s rdy2 p0 6 (led 06 )/s clk2 p0 5 (led 05 )/txd 2 p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 p2 5 /an 5 v ref reset p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 m37542mx-xxxsp m37542fxsp 32 14 15 16 p3 4 (led 14 ) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 package type: prdp0032ba-a (32p4b) p0 3 (led 03 )/tx out p0 2 (led 02 )/cmp 1 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 package type: pwqn0036ka-a (36pjw-a) p0 7 (led 07 )/s rdy2 p1 0 /rxd 1 /cap 0 p1 1 /txd 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 [n.c.] p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 p3 0 (led 10 )/cap 1 vss x out x in [n.c.] vcc cnvss reset p0 6 (led 06 )/s clk2 p3 4 (led 14 ) m37542mx-xxxhp m37542f8hp (note) p2 5 /an 5 v ref 36 [n.c.] [n.c.] p2 4 /an 4 p2 3 /an 3 p2 2 /an 2 p0 5 (led 05 )/txd 2 p0 4 (led 04 )/rxd 2 p0 3 (led 03 )/tx out p0 2 (led 02 )/cmp 1 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 27 26 25 20 19 21 24 23 22 9 8 7 6 5 3 14 2 31 30 29 28 35 34 33 32 10 11 12 13 14 15 16 17 18 n.c.: non connection note: only es version (mp: no plan)
7542 group rev.3.03 jul 11, 2008 page 4 of 117 rej03b0006-0303 fig. 5 pin configuration (package type: 42s1m) packa g e t yp e 42s1m 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 32 27 29 28 19 20 21 42 41 40 39 37 38 cnv ss x out x in v ss p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 vcc v ref p0 5 (led 05 )/txd 2 p1 2 /s clk1 p2 5 /an 5 p2 6 /an 6 p1 3 /s rdy1 p1 4 /cntr 0 nc p2 2 /an 2 nc p2 1 /an 1 p2 0 /an 0 p3 1 (led 11 )/cmp 2 p3 6 (led 16 )/int 1 p2 3 /an 3 p2 4 /an 4 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 reset m37542rss nc p3 5 (led 15 ) p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 nc p1 0 /r x d 1 /cap 0 p1 1 /t x d 1 nc nc p2 7 /an 7 p3 7 (led 17 )/int 0 p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out
7542 group rev.3.03 jul 11, 2008 page 5 of 117 rej03b0006-0303 t able 1 performance overview parameter 71 0.25 s (minimum instruction, oscillation frequency 8 mhz: double-speed mode) 8 mhz (max.) 8 k to 16 k bytes 384 to 512 bytes 16 k to 32 k + 4 k bytes 1024 bytes ?-bit ? 3, 5-bit ? 1 (8-bit ? 1, 6-bit ? 2, 5-bit ? 1 for 32-pin version and pwqn0036ka-a package version) 18 sources, 16 vectors ?-bit ? 2, 16-bit ? 2 4 channel 2 channel 8-bit ? 2 (uart or clock synchronous) 10-bit ? 8 channel (6 channel for 32-pin version and pwqn0036ka-a package version) 16-bit ? 1 built-in (external ceramic resonator or quartz-crystal oscillator, rc oscillation available) (low consumption current by on-chip oscillator available) 4.0 to 5.5 v 2.4 to 5.5 v 2.7 to 5.5 v 2.2 to 5.5 v 2.7 to 5.5 v 4.5 to 5.5 v 4.5 to 5.5 v 2.4 to 5.5 v 2.7 to 5.5 v 2.2 to 5.5 v 2.7 to 5.5 v 4.5 to 5.5 v 2.4 to 5.5 v 2.7 to 5.5 v 2.2 to 5.5 v 2.7 to 5.5 v 27.5 mw (typ.) 24.0 mw (typ.) -20 to 85 ? cmos silicon gate 32-pin plastic molded sdip/lqfp, 36-pin plastic molded ssop/wqfn number of basic instructions instruction execution time oscillation frequency memory sizes mask rom rom ram flash rom rom ram i/o port p0, p1, p2, p3 interrupts t imer output compare input capture serial interface a/d converter w atchdog timer clock generating circuit power source high-speed mode at 8mhz mask rom voltage middle-speed mode oscillation flash rom (at ceramic at 4mhz mask rom resonance) oscillation flash rom at 2mhz mask rom oscillation flash rom double-speed mode at 8mhz mask rom oscillation flash rom at 6.5mhz mask rom oscillation flash rom at 2mhz mask rom oscillation flash rom at 1mhz mask rom oscillation flash rom power source high-speed mode at 4mhz mask rom voltage middle-speed mode oscillation flash rom (at rc oscillation) at 2mhz mask rom oscillation flash rom at 1mhz mask rom oscillation flash rom power dissipation mask rom flash rom operating temperature range device structure package function
7542 group rev.3.03 jul 11, 2008 page 6 of 117 rej03b0006-0303 functional block fig. 6 functional block diagram (package type: plqp0032gb-a) functional block diagram (package type: plqp0032gb-a) x in out x si/o2(8) ram rom cpu a x y s pc h pc l ps v ss 11 reset 6 v cc 8 7 cnv ss p1(5) 30 28 26 29 27 32 31 p2(6) p3(6) 12 15 13 5 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 9 10 4 2 3 1 a/d converter (10) v ref watchdog timer reset 0 14 int 0 16 17 si/o1(8) cntr 0 i/o port p0 timer x (8) key-on wakeup prescaler x (8) timer b (16) p0(8) 25 23 21 19 24 22 20 18 timer 1 (8) prescaler 1 (8) timer a (16) input capture output compare int 1
7542 group rev.3.03 jul 11, 2008 page 7 of 117 rej03b0006-0303 fig. 7 functional block diagram (package type: prsp0036ga-a) functional block diagram (package type: prsp0036ga-a) x in out x si/o2(8) ram rom cpu a x y s pc h pc l ps v ss 18 reset 13 v cc 15 14 cnv ss p1(5) 31 35 2 36 76 p2(8) p3(8) 21 24 22 12 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 16 17 11 9 10 8 a/d converter (10) v ref watchdog timer reset 0 23 int 0 25 26 si/o1(8) cntr 0 i/o port p0 timer x (8) key-on wakeup prescaler x (8) timer b (16) p0(8) 34 32 30 28 33 31 29 27 timer 1 (8) prescaler 1 (8) timer a (16) int 1 19 20 5 4 input capture output compare
7542 group rev.3.03 jul 11, 2008 page 8 of 117 rej03b0006-0303 fig. 8 functional block diagram (package type: prdp0032ba-a) functional block diagram (package type: prdp0032ba-a) x in out x si/o2(8) ram rom cpu a x y s pc h pc l ps v ss 16 reset 11 v cc 13 12 cnv ss p1(5) 31 31 2 32 p2(6) p3(6) 17 20 18 10 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 14 15 a/d converter (10) v ref watchdog timer reset 0 19 int 0 21 22 si/o1(8) cntr 0 i/o port p0 timer x (8) key-on wakeup prescaler x (8) timer b (16) p0(8) 25 23 24 timer 1 (8) prescaler 1 (8) timer a (16) int 1 28 26 27 30 29 4 75 6 8 9 input capture output compare
7542 group rev.3.03 jul 11, 2008 page 9 of 117 rej03b0006-0303 fig. 9 functional block diagram (package type: pwqn0036ka-a) functional block diagram (package type: pwqn0036ka-a) x in out x si/o2(8) ram rom cpu a x y s pc h pc l ps v ss 13 reset 6 v cc 8 7 cnv ss p1(5) 34 32 30 33 31 36 35 p2(6) p3(6) 14 17 15 5 reset input i/o port p2 i/o port p1 i/o port p3 clock generating circuit clock input clock output 11 12 4 2 3 1 a/d converter (10) v ref watchdog timer reset 0 16 int 0 20 21 si/o1(8) cntr 0 i/o port p0 timer x (8) key-on wakeup prescaler x (8) timer b (16) p0(8) 25 23 24 22 timer 1 (8) prescaler 1 (8) timer a (16) input capture output compare int 1 29 27 28 26
7542 group rev.3.03 jul 11, 2008 page 10 of 117 rej03b0006-0303 pin description t able 2 pin description function mask rom version apply voltage of 2.2 to 5.5 v to vcc, and 0 v to vss. flash rom version apply voltage of 2.7 to 5.5 v to vcc, and 0 v to vss. ?eference voltage input pin for a/d converter. ?hip operating mode control pin, which is always connected to vss. ?eset input pin for active ? ?nput and output pins for main clock generating circuit. ?onnect a ceramic resonator or quartz crystal oscillator between the x in and x out pins. for using rc oscillator, short between the x in and x out pins, and connect the capacitor and resistor. ?f an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ?hen the on-chip oscillator is selected as the main clock, connect x in pin to v cc and leave x out open. function expect a port function name power source analog refer- ence voltage cnvss reset input clock input i/o port p0 i/o port p1 i/o port p2 (note 1) i/o port p3 (note 2) pin vcc, vss v ref cnvss reset x in p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out p0 4 (led 04 )/rxd 2 p0 5 (led 05 )/txd 2 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 p1 0 /rxd 1 /cap 0 p1 1 /txd 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 ?2 7 /an 7 p3 0 (led 10 )/cap 1 p3 1 (led 11 )/cmp 2 p3 2 (led 12 )/cmp 3 p3 3 (led 13 )/int 1 p3 4 (led 14 ) p3 5 (led 15 ) p3 6 (led 16 )/int 1 p3 7 (led 17 )/int 0 notes 1: p2 6 /an 6 and p2 7 /an 7 do not exist for the 32-pin version and pwqn0036ka-a package, so that port p2 is a 6-bit i/o port. 2: p3 5 and p3 6 /int 1 do not exist for the 32-pin version and pwqn0036ka-a package, so that port p3 is a 6-bit i/o port. ? capture function pin ? compare function pin ?timer x function pin ? serial i/o2 function pin ?serial i/o1 function pin ?capture function pin ?serial i/o1 function pin ?timer x function pin ?input pins for a/d converter ?capture function pin ?compare function pin ?interrupt input pin ?interrupt input pin ?-bit i/o port. ?/o direction register allows each pin to be individually pro- grammed as either input or output. ?mos compatible input level ?mos 3-state output structure ?hether a built-in pull-up resistor is to be used or not can be determined by program. ? high drive capacity for led drive port can be selected by program. ?-bit i/o port ?/o direction register allows each pin to be individually pro- grammed as either input or output. ?mos compatible input level ?mos 3-state output structure ?mos/ttl level can be switched for p1 0 , p1 2 and p1 3 ?-bit i/o port having almost the same function as p0 ?mos compatible input level ?mos 3-state output structure ?-bit i/o port ?/o direction register allows each pin to be individually pro- grammed as either input or output. ?mos compatible input level (cmos/ttl level can be switched for p3 6 and p3 7 ). ?mos 3-state output structure ?hether a built-in pull-up resistor is to be used or not can be determined by program. ? high drive capacity for led drive port can be selected by program. x out clock output ?key-input (key-on wake up interrupt input) pin
7542 group rev.3.03 jul 11, 2008 page 11 of 117 rej03b0006-0303 group expansion renesas plans to expand the 7542 group as follow: memory type support for mask rom version, flash memory version, and emu- lator mcu . memory size flash memory size ...................................... 16 to 32 k + 4 k bytes mask rom size ................................................... 8 k to 16 k bytes ram size ............................................................ 384 to 1024 bytes package prdp0032ba-a .................................. 32-pin plastic molded sdip plqp0032gb-a .......... 0.8 mm-pitch 32-pin plastic molded lqfp prsp0036ga-a .......... 0.8 mm-pitch 36-pin plastic molded ssop pwqn0036ka-a ........ 0.5 mm-pitch 36-pin plastic molded wqfn 42s1m .................................... 42-pin shrink ceramic piggy back fig. 10 memory expansion plan 384 32k +4k rom size (bytes) ram size (bytes) 512 1024 16k 0 8k m37542f8 m37542m2 16k +4k m37542f4 m37542m4
7542 group rev.3.03 jul 11, 2008 page 12 of 117 rej03b0006-0303 currently supported products are listed below. t able 3 list of supported products product rom size (bytes) rom size for user ( ) 8192 (8062) 16384 (16254) 16384 + 4096 (note 2) 32768 + 4096 (note 2) ram size (bytes) 384 512 1024 1024 1024 package prdp0032ba-a pwqn0036ka-a prsp0036ga-a plqp0032gb-a prdp0032ba-a pwqn0036ka-a prsp0036ga-a plqp0032gb-a prdp0032ba-a prsp0036ga-a plqp0032gb-a prdp0032ba-a prsp0036ga-a plqp0032gb-a pwqn0036ka-a 42s1m remarks mask rom version mask rom version mask rom version mask rom version mask rom version mask rom version mask rom version mask rom version flash memory version flash memory version flash memory version flash memory version flash memory version flash memory version flash memory version emulator mcu m37542m2-xxxsp m37542m2-xxxhp m37542m2-xxxfp m37542m2-xxxgp m37542m4-xxxsp m37542m4-xxxhp m37542m4-xxxfp m37542m4-xxxgp m37542f4sp m37542f4fp m37542f4gp m37542f8sp M37542F8FP m37542f8gp m37542f8hp (note 1) m37542rss notes 1: only es version (mp: no plan) 2: rom size includes the id code area.
7542 group rev.3.03 jul 11, 2008 page 13 of 117 rej03b0006-0303 b7 b0 x b7 b0 s b7 b0 y b7 b0 pc l processor status register (ps) carry flag b7 b0 b7 b0 a b15 pc h zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag program counter stack pointer index register y index register x accumulator c z i d b t v n functional description central processing unit (cpu) the mcu uses the standard 740 family instruction set. refer to the table of 740 family addressing modes and machine-language instructions or the series 740 user? manual for details on each instruction set. machine-resident 740 family instructions are as follows: 1. the fst and slw instructions cannot be used. 2. the mul and div instructions can be used. 3. the wit instruction can be used. 4. the stp instruction can be used. accumulator (a) the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. index register x (x), index register y (y) both index register x and index register y are 8-bit registers. in the index addressing modes, the value of the operand is added to the contents of register x or register y and specifies the real address. when the t flag in the processor status register is set to ?? the value contained in index register x becomes the address for the second operand. stack pointer (s) the stack pointer is an 8-bit register used during subroutine calls and interrupts. the stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. the lower eight bits of the stack address are determined by the contents of the stack pointer. the upper eight bits of the stack ad- dress are determined by the stack page selection bit. if the stack page selection bit is ?? then the ram in the zero page is used as the stack area. if the stack page selection bit is ?? then ram in page 1 is used as the stack area. the stack page selection bit is located in the sfr area in the zero page. note that the initial value of the stack page selection bit varies with each microcomputer type. also some microcom- puter types have no stack page selection bit and the upper eight bits of the stack address are fixed. the operations of pushing reg- ister contents onto the stack and popping them from the stack are shown in fig. 12. program counter (pc) the program counter is a 16-bit counter consisting of two 8-bit registers pc h and pc l . it is used to indicate the address of the next instruction to be executed. fig. 11 740 family cpu register structure
7542 group rev.3.03 jul 11, 2008 page 14 of 117 rej03b0006-0303 execute jsr on-going routine m (s) (pc h ) (s) (s ?1) m (s) (pc l ) execute rts (pc l )m (s) (s) (s ?1) (s) (s + 1) (s) (s + 1) (pc h )m (s) subroutine restore return address store return address on stack m (s) (ps) execute rti (ps) m (s) (s) (s ?1) (s) (s + 1) interrupt service routine restore contents of processor status register m (s) (pc h ) (s) (s ?1) m (s) (pc l ) (s) (s ?1) (pc l )m (s) (s) (s + 1) (s) (s + 1) (pc h )m (s) restore return address i flag ??to ?? fetch the jump vector store return address on stack store contents of processor status register on stack interrupt request (note) note : the condition to enable the interrupt interrupt enable bit is ? interrupt disable flag is ? t able 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 12 register push and pop at interrupt generation and subroutine call
7542 group rev.3.03 jul 11, 2008 page 15 of 117 rej03b0006-0303 processor status register (ps) the processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. branch operations can be performed by testing the carry (c) flag, zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. after reset, the interrupt disable (i) flag is set to ?? but all other flags are undefined. since the index x mode (t) and decimal mode (d) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. (1) carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. (2) zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is ?? and cleared if the result is anything other than ?? (3) interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is ?? when an interrupt occurs, this flag is automatically set to ??to prevent other interrupts from interfering until the current interrupt is serviced. (4) decimal mode flag (d) the d flag determines whether additions and subtractions are ex- ecuted in binary or decimal. binary arithmetic is executed when this flag is ?? decimal arithmetic is executed when it is ?? decimal correction is automatic in decimal mode. only the adc and sbc instructions can be used for decimal arithmetic. (5) break flag (b) the b flag is used to indicate that the current interrupt was gener- ated by the brk instruction. the brk flag in the processor status register is always ?? when the brk instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to ?? the saved processor status is the only place where the break flag is ever set. (6) index x mode flag (t) when the t flag is ?? arithmetic operations are performed be- tween accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. when the t flag is ?? direct arithmetic operations and direct data trans- fers are enabled between memory locations, i.e. between memory and memory, memory and i/o, and i/o and i/o. in this case, the result of an arithmetic operation performed on data in memory lo- cation 1 and memory location 2 is stored in memory location 1. the address of memory location 1 is specified by index register x, and the address of memory location 2 is specified by normal ad- dressing modes. (7) overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location oper- ated on by the bit instruction is stored in the overflow flag. (8) negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. t able 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag i flag sei cli d flag sed cld b flag t flag set clt v flag clv n flag
7542 group rev.3.03 jul 11, 2008 page 16 of 117 rej03b0006-0303 [cpu mode register] cpum the cpu mode register contains the stack page selection bit, etc.. this register is allocated at address 003b 16 . switching method of cpu mode register switch the cpu mode register (cpum) at the head of program af- ter releasing reset in the following method. fig. 14 switching method of cpu mode register fig. 13 structure of cpu mode register oscillation mode selection bit (note 1) 0 : ceramic oscillation 1 : rc oscillation cpu mode register (cpum: address 003b 16 , initial value: 80 16 ) stack page selection bit 0 : 0 page 1 : 1 page clock division ratio selection bits b7 b6 0 0 : f( ) = f(x in )/2 (high-speed mode) 0 1 : f( ) = f(x in )/8 (middle-speed mode) 1 0 : applied from on-chip oscillator 1 1 : f( ) = f(x in ) (double-speed mode)(note 2) on-chip oscillator oscillation control bit 0 : on-chip oscillator oscillation enabled 1 : on-chip oscillator oscillation stop x in oscillation control bit 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop processor mode bits (note 1) b1 b0 0 0 single-chip mode 0 1 1 0 1 1 not available b7 b0 2: these bits are used only when a ceramic oscillation is selected. note 1: these bits can be rewritten only once after releasing reset. after rewriting it is disable to write any data to bits. however, by reset bits are initialized and can be rewritten, again. (it is not disable to write any data to bits for emulator mcu ?37542rss?) do not use these when an rc oscillation is selected. after releasing reset switch the oscillation mode selection bit (bit 5 of cpum) switch the clock division ratio selection bits (bits 6 and 7 of cpum) main routine start with an on-chip oscillator an initial value is set as a ceramic oscillation mode. when it is switched to an rc oscillation, its oscillation starts. select 1/1, 1/2, 1/8 or on-chip oscillator. wait by on-chip oscillator operation until establishment of oscillator clock when using a ceramic oscillation, wait until establlishment of oscillation from oscillation starts. when using an rc oscillation, wait time is not required basically (time to execute the instruction to switch from an on-chip oscillator meets the requirement). note: after system is released from reset, an on-chip oscillator turns active automatically and system operation is started.
7542 group rev.3.03 jul 11, 2008 page 17 of 117 rej03b0006-0303 memory special function register (sfr) area the sfr area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for a stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 2 bytes of rom are reserved for device testing and the rest is a user area for storing programs. the reserved rom area can program/erase in the flash memory version. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page the 256 bytes from addresses 0000 16 to 00ff 16 are called the zero page area. the internal ram and the special function regis- ters (sfr) are allocated to this area. the zero page addressing mode can be used to specify memory and register addresses in the zero page area. access to this area with only 2 bytes is possible in the zero page addressing mode. special page the 256 bytes from addresses ff00 16 to ffff 16 are called the special page area. the special page addressing mode can be used to specify memory addresses in the special page area. ac- cess to this area with only 2 bytes is possible in the special page addressing mode. fig. 15 memory map diagram 0100 16 0000 16 0040 16 0440 16 ff00 16 ffdc 16 fffe 16 ffff 16 384 512 1024 xxxx 16 01bf 16 023f 16 043f 16 8192 16384 32768 e000 16 c000 16 8000 16 e080 16 c080 16 8080 16 yyyy 16 zzzz 16 ram ro m reserved area sfr area not used interrupt vector area rom area reserved rom area (128 bytes) zero page special page ram area ram capacity (bytes) address xxxx 16 rom capacity (bytes) address yyyy 16 reserved rom area address zzzz 16 not used sfr area (note 1) 0fe0 16 0fff 16 notes 1: only flash memory version has this sfr area. 2: the reserved rom area can program/erase in the flash memory version. note the difference of the mask version.
7542 group rev.3.03 jul 11, 2008 page 18 of 117 rej03b0006-0303 fig. 16 memory map of special function register (sfr) notes 1: do not access to the sfr area including nothing. 2: only flash memory version has this sfr area. 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) pull-up control register (pull) transmit 1 /receive 1 buffer register (tb1/rb1) serial i/o1 status register (sio1sts) serial i/o1 control register (sio1con) uart1 control register (uart1con) baud rate generator 1 (brg1) port p1p3 control register (p1p3c) 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 timer count source set register (tcss) a/d conversion register (low-order) (adl) prescaler 1 (pre1) timer 1 (t1) timer x mode register (txm) prescaler x (prex) timer x (tx) serial i/o2 control register (sio2con) uart2 control register (uart2con) a/d control register (adcon) a/d conversion register (high-order) (adh) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) timer a, b mode register (tabm) capture/compare port register (ccpr) timer source selection register (tmsr) capture mode register (capm) compare output mode register (cmom) capture/compare status register (ccsr) compare interrupt source set register (cisr) interrupt request register 2 (ireq2) interrupt control register 2 (icon2) on-chip oscillation division ratio selection register (rodr) baud rate generator 2 (brg2) timer a (low-order) (tal) timer a (high-order) (tah) timer b (low-order) (tbl) timer b (high-order) (tbh) transmit 2 / receive 2 buffer register (tb2/rb2) serial i/o2 status register (sio2sts) port p0p3 drive capacity control register (dccr) compare register re-load register (cmpr) capture software trigger register (cstr) capture/compare register r/w pointer (ccrp) compare register (high-order) (cmph) compare register (low-order) (cmpl) capture register 1 (high-order) (cap1h) capture register 1 (low-order) (cap1l) capture register 0 (high-order) (cap0h) capture register 0 (low-order) (cap0l) interrupt source set register (intset) interrupt source discrimination register (intdis) reserved reserved reserved 0fe0 16 0fe1 16 flash memory control register 0 (fmcr0) (note 2) flash memory control register 1 (fmcr1) (note 2) 0fe2 16 flash memory control register 2 (fmcr2) (note 2)
7542 group rev.3.03 jul 11, 2008 page 19 of 117 rej03b0006-0303 i/o ports [direction registers] pid the i/o ports have direction registers which determine the input/ output direction of each pin. each bit in a direction register corre- sponds to one pin, and each pin can be set to be input or output. when ??is set to the bit corresponding to a pin, this pin becomes an output port. when ??is set to the bit, the pin becomes an in- put port. when data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. pins set to input are float- ing, and permit reading pin values. if a pin set to input is written to, only the port latch is written to and the pin remains floating. note: p2 6 /an 6 , p2 7 /an 7 , p3 5 and p3 6 do not exist for the 32-pin version and pwqn0036ka-a package. accordingly, the following settings are required; ?select p3 3 for the int 1 function. ?set direction registers of ports p2 6 and p2 7 to output. ?set direction registers of ports p3 5 and p3 6 to output. [port p0p3 drive capacity control register] dccr by setting the port p0p3 drive capacity control register (address 0015 16 ), the drive capacity of the n-channel output transistor for the port p0 and port p3 can be selected. [pull-up control register] pull by setting the pull-up control register (address 0016 16 ), ports p0 and p3 can exert pull-up control by program. however, pins set to output are disconnected from this control and cannot exert pull-up control. [port p1p3 control register] p1p3c by setting the port p1p3 control register (address 0017 16 ), a cmos input level or a ttl input level can be selected for ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 by program. fig. 19 structure of port p1p3 control register fig. 18 structure of pull-up control register port p1p3 control register (p1p3c: address 0017 16 , initial value: 00 16 ) b7 b0 note: keep setting the p3 6 /int 1 input level selection bit to ??(initial value) for 32-pin version and 36pjw-a package. not used 1 : ttl level 0 : cmos level p1 0 ,p1 2 ,p1 3 input level selection bit 1 : ttl level 0 : cmos level p3 6 /int 1 input level selection bit 1 : ttl level 0 : cmos level p3 7 /int 0 input level selection bit pull-up c ontrol register (pull: address 0016 16 , in itial value: 00 16 ) p 0 0 p u l l - u p c o n t r o l b i t p 0 1 , p 0 2 p u l l - u p c o n t r o l b i t p 0 3 ? 0 7 p u l l - u p c o n t r o l b i t p 3 0 p u l l - u p c o n t r o l b i t p 3 1 , p 3 2 p u l l - u p c o n t r o l b i t p 3 3 p u l l - u p c o n t r o l b i t p 3 4 , p 3 5 p u l l - u p c o n t r o l b i t p 3 6 , p 3 7 p u l l - u p c o n t r o l b i t b 7 b 0 0 : p u l l - u p o f f 1 : p u l l - u p o n n o t e : p i n s s e t t o o u t p u t p o r t s a r e d i s c o n n e c t e d f r o m p u l l - u p c o n t r o l . p o r t p 0 p 3 d r i v e c a p a c i t y c o n t r o l r e g i s t e r ( d c c r : a d d r e s s 0 0 1 5 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) p o r t p 0 0 d r i v e c a p a c i t y b i t p o r t s p 0 1 , p 0 2 d r i v e c a p a c i t y b i t p o r t s p 0 3 ? 0 7 d r i v e c a p a c i t y b i t p o r t p 3 0 d r i v e c a p a c i t y b i t p o r t s p 3 1, p 3 2 d r i v e c a p a c i t y b i t p o r t p 3 3 d r i v e c a p a c i t y b i t p o r t s p 3 4 , p 3 5 d r i v e c a p a c i t y b i t p o r t s p 3 6 , p 3 7 d r i v e c a p a c i t y b i t b 7 b 0 0 : l o w 1 : h i g h n o t e : n u m b e r o f l e d d r i v e p o r t ( d r i v e c a p a c i t y i s h i g h ) i s 8 - p o r t . fig. 17 structure of port p0p3 drive capacity control register
7542 group rev.3.03 jul 11, 2008 page 20 of 117 rej03b0006-0303 t able 6 i/o port function table pin p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out p0 4 (led 04 )/rxd 2 p0 5 (led 05 )/txd 2 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 p1 0 /rxd 1 /cap 0 p1 1 /txd 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 ?2 7 /an 7 p3 0 (led 10 )/cap 1 p3 1 (led 11 )/cmp 2 p3 2 (led 12 )/cmp 3 p3 3 (led 13 )/int 1 p3 4 (led 14 ) p3 5 (led 15 ) p3 6 (led 16 )/int 1 p3 7 (led 17 )/int 0 i/o format ?mos compatible input level ( note 1 ) ?mos 3-state output non-port function ?capture function input ?key input interrupt ?compare function output ?key input interrupt ?timer x function output ?key input interrupt ?serial i/o2 function input/output ?key input interrupt ?serial i/o1 function input ?capture function input ?serial i/o1 function input/output ?timer x function input/output ?external interrupt input ?a/d conversion input ?capture function input ?compare function output ?external interrupt input ?external interrupt input sfrs related each pin capture/compare port register interrupt edge selection register pull-up control register port p0p3 drive capacity control register capture/compare port register pull-up control register port p0p3 drive capacity control register t imer x mode register pull-up control register port p0p3 drive capacity control register serial i/o2 control register interrupt edge selection register pull-up control register port p0p3 drive capacity control register serial i/o2 control register pull-up control register port p0p3 drive capacity control register serial i/o2 control register interrupt edge selection register pull-up control register port p0p3 drive capacity control register serial i/o2 control register pull-up control register port p0p3 drive capacity control register serial i/o1 control register capture/compare port register port p1p3 control register serial i/o1 control register serial i/o1 control register port p1p3 control register serial i/o1 control register port p1p3 control register t imer x mode register a/d control register capture/compare port register pull-up control register port p0p3 drive capacity control register capture/compare port register pull-up control register port p0p3 drive capacity control register interrupt edge selection register pull-up control register port p0p3 drive capacity control register pull-up control register port p0p3 drive capacity control register interrupt edge selection register pull-up control register port p0p3 drive capacity control register port p1p3 control register diagram no. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) notes 1: ports p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 are cmos/ttl level. 2: p2 6/ an 6 and p2 7 /an 7 do not exist for the 32-pin version and pwqn0036ka-a package. 3: p3 5 and p3 6 /int 1 do not exist for the 32-pin version and pwqn0036ka-a package. name i/o port p0 i/o port p1 i/o port p2 ( note 2 ) i/o port p3 ( note 3 )
7542 group rev.3.03 jul 11, 2008 page 21 of 117 rej03b0006-0303 fig. 20 block diagram of ports (1) (1) port p0 0 direction register data bus port latch pull-up control to key input interrupt generating circuit capture 0 input p0 0 key-on wakeup selection bit drive capacity control capture 0 input control (2) ports p0 1, p0 2 compare output direction register data bus port latch pull-up control to key input interrupt generating circuit compare output control drive capacity control (3) port p0 3 timer output direction register data bus port latch pull-up control to key input interrupt generating circuit p0 3 /tx out output valid drive capacity control (4) port p0 4 serial i/o2 input direction register data bus port latch pull-up control to key input interrupt generating circuit serial i/o2 enable bit drive capacity control p0 4 key-on wakeup selection bit receive enable bit (5) port p0 5 serial i/o2 output direction register data bus port latch pull-up control to key input interrupt generating circuit serial i/o2 enable bit drive capacity control transmit enable bit (6) port p0 6 serial i/o2 clock output direction register data bus port latch pull-up control to key input interrupt generating circuit serial i/o2 mode selection bit drive capacity control serial i/o2 enable bit serial i/o2 synchronous clock selection bit serial i/o2 clock input p0 6 key-on wakeup selection bit serial i/o2 enable bit (7) port p0 7 serial i/o2 ready output direction register data bus port latch pull-up control to key input interrupt generating circuit serial i/o2 mode selection bit serial i/o2 enable bit s rdy2 output enable bit drive capacity control
7542 group rev.3.03 jul 11, 2008 page 22 of 117 rej03b0006-0303 fig. 21 block diagram of ports (2) (8) port p1 0 direction register data bus port latch serial i/o1 enable bit receive enable bit serial i/o1 input capture 0 input control p1 0 , p1 2 , p1 3 input level selection bit capture 0 input p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. when the ttl level is selected , there is no h y steresis characteristics. (9) port p1 1 data bus port latch serial i/o1 output p1 1 /t x d 1 p-channel output disable bit direction register serial i/o1 enable bit transmit enable bit (10) port p1 2 serial i/o1 clock output serial i/o1 mode selection bit serial i/o1 enable bit serial i/o1 enable bit serial i/o1 synchronous clock selection bit direction register data bus port latch serial i/o1 clock input p1 0 , p1 2 , p1 3 input level selection bit * (12) port p1 4 data bus serial i/o1 ready output port latch direction register cntr 0 interrupt input timer output p1 0 , p1 2 , p1 3 input level selection bit serial i/o1 mode selection bit serial i/o1 enable bit s rdy1 output enable bit data bus port latch direction register * (11) port p1 3 data bus port latch direction register a/d converter input analog input pin selection bit (13) ports p2 0 ?2 7 * * pulse output mode
7542 group rev.3.03 jul 11, 2008 page 23 of 117 rej03b0006-0303 fig. 22 block diagram of ports (3) (14) port p3 0 direction register data bus port latch pull-up control capture 1 input drive capacity control capture 1 input control (15) ports p3 1, p3 2 compare output direction register data bus port latch pull-up control compare output control drive capacity control (16) port p3 3 direction register data bus port latch pull-up control int 1 input control drive capacity control int 1 input (17) ports p3 4, p3 5 direction register data bus port latch pull-up control drive capacity control (19) port p3 7 direction register data bus port latch pull-up control drive capacity control int 0 input p3 input level selection bit * p1 0 , p1 2 , p1 3 , p3 6 , and p3 7 input level are switched to the cmos/ttl level by the port p1p3 control register. * when the ttl level is selected , there is no h y steresis characteristics. (18) port p3 6 direction register data bus port latch pull-up control drive capacity control int 1 input p3 input level selection bit * int 1 input control
7542 group rev.3.03 jul 11, 2008 page 24 of 117 rej03b0006-0303 t ermination of unused pins ?termination of common pins i/o ports: select an input port or an output port and follow each processing method. output ports: open. input ports: if the input level become unstable, through current flow to an input circuit, and the power supply current may increase. pin p0 0 /cap 0 p0 1 /cmp 0 p0 2 /cmp 1 p0 3 /tx out p0 4 /rxd 2 p0 5 /txd 2 p0 6 /s clk2 p0 7 /s rdy2 p1 0 /rxd 1 /cap 0 p1 1 /txd 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 ?2 7 /an 7 p3 0 /cap 1 p3 1 /cmp 2 p3 2 /cmp 3 p3 3 /int 1 p3 4 p3 5 p3 6 /int 1 p3 7 /int 0 v ref x in x out t ermination 1 (recommend) i/o port connect to vss. when only on-chip oscillator is used, connect to v cc through a resistor. when external clock is input or when on-chip oscillator is used, open. t ermination 2 when selecting cap function, per- form termination of input port. when selecting cmp 0 function, perform termination of output port. when selecting cmp 1 function, perform termination of output port. when selecting tx out function, perform termination of output port. when selecting rxd 2 function, perform termination of input port. when selecting txd 2 f unction, perform termination of output port. when selecting external clock input, perform termination of output port. when selecting s rdy2 function, perform termination of output port. when selecting rxd 1 function, perform termination of input port. when selecting txd 1 f unction, perform termination of output port. when selecting external clock input, perform termination of input port. when selecting s rdy1 function, perform termination of output port. when selecting cntr input function, perform termination of input port. when selecting an function, per- form termination of input port. when selecting cap function, per- form termination of input port. when selecting cmp 2 function, perform termination of output port. when selecting cmp 3 function, perform termination of output port. when selecting int function, per- form termination of input port. - - when selecting int function, per- form termination of input port. when selecting int function, per- form termination of input port. - - - t ermination 3 - - - - - - when selecting internal clock output, perform termination of output port. - when selecting cap function, per- form termination of input port. - when selecting internal clock output, perform termination of output port. - when selecting cntr output function, perform termination of output port. - - - - - - - - - - - - t ermination 4 when selecting key-on wakeup function, per- form termination of input port. - - - - - - - - - - - - - - - - t able 7 termination of unused pins especially, when expecting low consumption current (at stp or wit instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). we recommend processing unused pins through a resistor which can secure i oh(avg) or i ol(avg) . because, when an i/o port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc.
7542 group rev.3.03 jul 11, 2008 page 25 of 117 rej03b0006-0303 interrupts the 7542 group interrupts are vector interrupts with a fixed prior- ity scheme, and generated by 16 sources among 18 sources: 6 external, 11 internal, and 1 software. the interrupt sources, vector addresses (1) , and interrupt priority are shown in table 8. each interrupt except the brk instruction interrupt has the inter- rupt request bit and the interrupt enable bit. these bits and the interrupt disable flag (i flag) control the acceptance of interrupt re- quests. figure 23 shows an interrupt control diagram. an interrupt request is accepted when all of the following condi- tions are satisfied: ?interrupt disable flag.................................? ?interrupt request bit...................................? ?interrupt enable bit....................................? though the interrupt priority is determined by hardware, priority processing can be performed by software using the above bits and flag. t able 8 interrupt vector addresses and priority v ector addresses (note 1) high-order priority low-order interrupt request generating conditions remarks interrupt source fffc 16 fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 fffd 16 fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 notes1: vector addresses contain internal jump destination addresses. 2: reset function in the same way as an interrupt with the highest priority. 3: key-on wakeup interrupt and uart1 bus collision detection interrupt can be enabled by setting of interrupt source set register. the occurrence of these interrupts are discriminated by interrupt source discrimination register. 4: a/d conversion interrupt and timer 1 interrupt can be enabled by setting of interrupt source set register. the occurrence of t hese interrupts are dis- criminated by interrupt source discrimination register. non-maskable v alid only when serial i/o1 is selected v alid only when serial i/o1 is selected v alid only when serial i/o2 is selected v alid only when serial i/o2 is selected external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (valid at falling edge) when uart1 bus collision detection interrupt is enabled. external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (active edge selectable) compare interrupt source is selected. stp release timer underflow non-maskable software interrupt at reset input at completion of serial i/o1 data receive at completion of serial i/o1 transmit shift or when transmit buffer is empty at completion of serial i/o2 data receive at completion of serial i/o2 transmit shift or when transmit buffer is empty at detection of either rising or falling edge of int 0 input at detection of either rising or falling edge of int 1 input at falling of conjunction of input logical level for port p0 (at input) at detection of uart1 bus collision detection at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of capture 0 input at detection of either rising or falling edge of capture 1 input at compare matched at timer x underflow at timer a underflow at timer b underflow at completion of a/d conversion at timer 1 underflow at brk instruction execution 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 reset (note 2) serial i/o1 receive serial i/o1 transmit serial i/o2 receive serial i/o2 transmit int 0 int 1 key-on wake-up/ uart1 bus collision detection (note 3) cntr 0 capture 0 capture 1 compare t imer x tim er a t imer b a/d conversion/ ti mer 1 (note 4) brk instruction
7542 group rev.3.03 jul 11, 2008 page 26 of 117 rej03b0006-0303 fig. 23 interrupt control interrupt request bit interrupt enable bit interrupt disable flag i brk instruction reset interrupt acceptance ?interrupt disable flag the interrupt disable flag is assigned to bit 2 of the processor sta- tus register. this flag controls the acceptance of all interrupt requests except for the brk instruction. when this flag is set to ?? the acceptance of interrupt requests is disabled. when it is set to ?? the acceptance of interrupt requests is enabled. this flag is set to ??with the sei instruction and set to ??with the cli in- struction. when an interrupt request is accepted, the contents of the proces- sor status register are pushed onto the stack while the interrupt disable flag remains set to ?? subsequently, this flag is automati- cally set to ??and multiple interrupts are disabled. to use multiple interrupts, set this flag to ??with the cli instruc- tion within the interrupt processing routine. the contents of the processor status register are popped off the stack with the rti instruction. ?interrupt request bits once an interrupt request is generated, the corresponding inter- rupt request bit is set to ??and remains ??until the request is accepted. when the request is accepted, this bit is automatically set to ?? each interrupt request bit can be set to ?? but cannot be set to ?? by software. ?interrupt enable bits the interrupt enable bits control the acceptance of the corre- sponding interrupt requests. when an interrupt enable bit is set to ?? the acceptance of the corresponding interrupt request is dis- abled. if an interrupt request occurs in this condition, the corresponding interrupt request bit is set to ?? but the interrupt request is not accepted. when an interrupt enable bit is set to ?? the acceptance of the corresponding interrupt request is enabled. each interrupt enable bit can be set to ??or ??by software. the interrupt enable bit for an unused interrupt should be set to ?? ?interrupt enable setting the following interrupt sources can be set to valid or invalid by the interrupt source set register (000a 16 ). ?key-on wakeup ?uart1 bus collision detection interrupt ?a/d conversion ?timer 1 interrupt ?external interrupt pin selection for the external interrupt int 1 , the external input pin p3 3 or p3 6 can be selected by the int 1 input port selection bit in the interrupt edge selection register (bit 2 of address 003a 16 ). however, since there is no p3 6 /int 1 pin in the 32-pin version pwqn0036ka-a package, select p3 3 /int 1 pin. by the key-on wakeup selection bit, enable/disable of a key-on wakeup of p0 0 , p0 4 , and p0 6 pins can be selected, respectively.
7542 group rev.3.03 jul 11, 2008 page 27 of 117 rej03b0006-0303 b7 b0 interrupt control register 1 serial i/o1 receive interrupt enable bit 0 : interrupts disabled 1 : interrupts enabled (icon1 : address 003e 16 , initial value : 00 16 ) b7 b0 interrupt control register 2 capture 0 interrupt enable bit 0 : interrupts disabled 1: interrupts enabled (icon2 : address 003f 16 , initial value : 00 16 ) interrupt request register 2 0 : no interrupt request issued 1 : interrupt request issued (ireq2 : address 003d 16 , initial value : 00 16 ) b7 b0 capture 0 interrupt request bit interrupt request register 1 serial i/o1 receive interrupt request bit 0 : no interrupt request issued 1 : interrupt request issued (ireq1 : address 003c 16 , initial value : 00 16 ) b7 b0 not used (returns ??when read) (do not write ??to this bit.) a/d conversion/timer 1 interrupt enable bit timer b interrupt enable bit timer a interrupt enable bit timer x interrupt enable bit compare interrupt enable bit capture 1 interrupt enable bit cntr 0 interrupt enable bit key-on wake up/uart1 bus collision detection interrupt enable bit int 1 interrupt enable bit int 0 interrupt enable bit serial i/o2 transmit interrupt enable bit serial i/o2 receive interrupt enable bit serial i/o1 transmit interrupt enable bit not used (returns ??when read) (do not write ??to this bit.) a/d conversion/timer 1 interrupt request bit timer b interrupt request bit timer a interrupt request bit timer x interrupt request bit compare interrupt request bit capture 1 interrupt request bit cntr 0 interrupt request bit key-on wake up/uart1 bus collision detection interrupt request bit int 1 interrupt request bit int 0 interrupt request bit serial i/o2 transmit interrupt request bit serial i/o2 receive interrupt request bit serial i/o1 transmit interrupt request bit interrupt source set register (intset: address 000a 16 , initial value: 00 16 ) key-on wakeup interrupt valid bit b7 b0 interrupt source discrimination register (intdis: address 000b 16 , initial value: 00 16 ) key-on wakeup interrupt discrimination bit b7 b0 interrupt edge selection register (intedge : address 003a 16 , initial value: 00 16 ) b7 b0 not used (returns ??when read) timer 1 interrupt valid bit a/d conversion interrupt valid bit uart1 bus collision detection interrupt valid bit 1: interrupt valid 0: interrupt invalid 1 : interrupt request issued 0 : no interrupt request issued not used (returns ??when read) timer 1 interrupt discrimination bit a/d conversion interrupt discrimination bit uart1 bus collision detection interrupt discrimination bit int 0 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 1 interrupt edge selection bit 0 : falling edge active 1 : rising edge active int 1 input port selection bit ( note 1 ) 0 : p3 6 1 : p3 3 not used (returns ??when read) p0 0 key-on wakeup selection bit 0 : key-on wakeup enabled 1 : key-on wakeup disabled p0 4 key-on wakeup selection bit 0 : key-on wakeup enabled 1 : key-on wakeup disabled p0 6 key-on wakeup selection bit 0 : key-on wakeup enabled 1 : ke y -on wakeu p disabled fig. 24 structure of interrupt-related registers note 1: p3 6 does not exist for the 32-pin version and the pwqn0036ka-a package. select p3 3 for the int 1 function.
7542 group rev.3.03 jul 11, 2008 page 28 of 117 rej03b0006-0303 ?interrupt request generation, acceptance, and handling interrupts have the following three phases. (i) interrupt request generation an interrupt request is generated by an interrupt source (ex- ternal interrupt signal input, timer underflow, etc.) and the corresponding request bit is set to ?? (ii) interrupt request acceptance based on the interrupt acceptance timing in each instruction cycle, the interrupt control circuit determines acceptance con- ditions (interrupt request bit, interrupt enable bit, and interrupt disable flag) and interrupt priority levels for accepting interrupt requests. when two or more interrupt requests are generated simultaneously, the highest priority interrupt is accepted. the value of the interrupt request bit for an unaccepted interrupt remains the same and acceptance is determined at the next interrupt acceptance timing point. (iii) handling of accepted interrupt request the accepted interrupt request is processed. figure 25 shows the time up to execution in the interrupt process- ing routine, and figure 26 shows the interrupt sequence. figure 27 shows the timing of interrupt request generation, inter- rupt request bit, and interrupt request acceptance. ?interrupt handling execution when interrupt handling is executed, the following operations are performed automatically. (1) once the currently executing instruction is completed, an in- terrupt request is accepted. (2) the contents of the program counters and the processor sta- tus register at this point are pushed onto the stack area in order from 1 to 3. 1.high-order bits of program counter (pch) 2.low-order bits of program counter (pcl) 3.processor status register (ps) (3) concurrently with the push operation, the jump address of the corresponding interrupt (the start address of the interrupt pro- cessing routine) is transferred from the interrupt vector to the program counter. (4) the interrupt request bit for the corresponding interrupt is set to ?? also, the interrupt disable flag is set to ??and multiple interrupts are disabled. (5) the interrupt routine is executed. (6) when the rti instruction is executed, the contents of the reg- isters pushed onto the stack area are popped off in the order from 3 to 1. then, the routine that was before running interrupt processing resumes. as described above, it is necessary to set the stack pointer and the jump address in the vector area corresponding to each inter- rupt to execute the interrupt processing routine. notes on interrupts when setting the followings, the interrupt request bit may be set to ?? ?hen switching external interrupt active edge related registers: interrupt edge selection register (address 003a 16 ) t imer x mode register (address 002b 16 ) capture mode register (address 0020 16 ) when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge select bit (active edge switch bit, trigger mode bit). ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). main routine interrupt handling routine interrupt request generated interrupt request acceptance interrupt routine starts interrupt sequence 7 cycles 0 to 16* cycles 7 to 23 cycles * when executing div instruction stack push vector fetch fig. 25 time up to execution in interrupt routine
7542 group rev.3.03 jul 11, 2008 page 29 of 117 rej03b0006-0303 fig. 27 timing of interrupt request generation, interrupt request bit, and interrupt acceptance instruction cycle push onto stack vector fetch instruction cycle internal clock sync t1 ir1 t2 ir2 t3 ? ? t1 t2 t3 : interrupt acceptance timing points ir1 ir2 : timings points at which the interrupt request bit is set to ?? note : period 2 indicates the last cycle during one instruction cycle. (1) the interrupt request bit for an interrupt request generated during period 1 is set to ??at timing point ir1. (2) the interrupt request bit for an interrupt request generated during period 2 is set to ??at timing point ir1 or ir2. the timing point at which the bit is set to ??varies depending on conditions. when two or more interrupt requests are generated during the period 2, each request bit may be set to ??at timing point ir1 or ir2 separately. fig. 26 interrupt sequence sync rd wr address bus data bus pc not used s,sps s-1,sps s-2,sps b l b h a l ,a h pc h pc l ps a l a h sync : cpu operation code fetch cycle (this is an internal signal that cannot be observed from the external unit.) b l , b h : vector address of each interrupt a l , a h : jump destination address of each interrupt sps : ?0 16 ?or ?1 16 ([sps] is a page selected by the stack page selection bit of cpu mode register.) push onto stack vector fetch execute interrupt routine
7542 group rev.3.03 jul 11, 2008 page 30 of 117 rej03b0006-0303 key input interrupt (key-on wake-up) a key-on wake-up interrupt request is generated by applying ? level to any pin of port p0 that has been set to input mode. in other words, it is generated when the and of input level goes from ??to ?? an example of using a key input interrupt is shown in figure 28, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports p0 0 to p0 3 as input ports. fig. 28 connection example when using key input interrupt and port p0 block diagram port pxx ??level output pull register bit 3 = ?? port p0 7 latch port p0 7 direction register = ? ** * p0 7 output key input interrupt request port p0 input read circuit * p-channel transistor for pull-up ** cmos out p ut buffer pull register bit 3 = ?? port p0 6 latch port p0 6 direction register = ? ** * p0 6 output pull register bit 3 = ?? port p0 5 latch port p0 5 direction register = ? ** * p0 5 output pull register bit 3 = ?? port p0 4 latch port p0 4 direction register = ? ** * p0 4 output pull register bit 2 = ?? port p0 3 latch port p0 3 direction register = ? ** * p0 3 input pull register bit 2 = ?? port p0 2 latch port p0 2 direction register = ? ** * p0 2 input pull register bit 1 = ?? port p0 1 latch port p0 1 direction register = ? ** * p0 1 input pull register bit 0 = ?? port p0 0 latch port p0 0 direction register = ? ** * p0 0 input falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection falling edge detection port p0 0 key-on wakeup selection bit port p0 6 key-on wakeup selection bit port p0 4 key-on wakeup selection bit
7542 group rev.3.03 jul 11, 2008 page 31 of 117 rej03b0006-0303 t imers the 7542 group has 4 timers: timer 1, timer x, timer a and timer b. the division ratio of every timer and prescaler is 1/(n+1) provided that the value of the timer latch or prescaler is n. all the timers are down count timers. when a timer reaches ?? an underflow occurs at the next count pulse, and the corresponding timer latch is reloaded into the timer. when a timer underflows, the interrupt request bit corresponding to each timer is set to ?? ?frequency divider for timer according to the clock division selection bits (b7 and b6) of cpu mode register (003b 16 ), the count source of frequency divider is set as follows; b7b6 = ?0?high-speed), ?1?middle-speed), ?1?double-speed): x in b7b6 = ?0?on-chip oscillator): on-chip oscillator tim er 1 t imer 1 is an 8-bit timer and counts the prescaler output. when timer 1 underflows, the timer 1 interrupt request bit is set to ?? prescaler 1 is an 8-bit prescaler and counts the signal which is the oscillation frequency divided by 16. prescaler 1 and timer 1 have the prescaler 1 latch and the timer 1 latch to retain the reload value, respectively. the value of prescaler 1 latch is set to prescaler 1 when prescaler 1 underflows. the value of timer 1 latch is set to timer 1 when timer 1 underflows. when writing to prescaler 1 (pre1) is executed, the value is writ- ten to both the prescaler 1 latch and prescaler 1. when writing to timer 1 (t1) is executed, the value is written to both the timer 1 latch and timer 1. when reading from prescaler 1 (pre1) and timer 1 (t1) is ex- ecuted, each count value is read out. t imer 1 always operates in the timer mode. prescaler 1 counts the signal which is the oscillation frequency di- vided by 16. each time the count clock is input, the contents of prescaler 1 is decremented by 1. when the contents of prescaler 1 reach ?0 16 ? an underflow occurs at the next count clock, and the prescaler 1 latch is reloaded into prescaler 1 and count contin- ues. the division ratio of prescaler 1 is 1/(n+1) provided that the value of prescaler 1 is n. the contents of timer 1 is decremented by 1 each time the under- flow signal of prescaler 1 is input. when the contents of timer 1 reach ?0 16 ? an underflow occurs at the next count clock, and the timer 1 latch is reloaded into timer 1 and count continues. the di- vision ratio of timer 1 is 1/(m+1) provided that the value of timer 1 is m. accordingly, the division ratio of prescaler 1 and timer 1 is 1/((n+1) ? (m+1)) provided that the value of prescaler 1 is n and the value of timer 1 is m. t imer 1 cannot stop counting by software. ti mer x t imer x is an 8-bit timer and counts the prescaler x output. when timer x underflows, the timer x interrupt request bit is set to ?? prescaler x is an 8-bit prescaler and counts the signal selected by the timer x count source selection bit. prescaler x and timer x have the prescaler x latch and the timer x latch to retain the reload value, respectively. the value of prescaler x latch is set to prescaler x when prescaler x underflows. the value of timer x latch is set to timer x when t imer x underflows. when writing to prescaler x (prex) is executed, the value is writ- ten to both the prescaler x latch and prescaler x. when writing to timer x (tx) is executed, the value is written to both the timer x latch and timer x. when reading from prescaler x (prex) and timer x (tx) is ex- ecuted, each count value is read out. t imer x can be selected in one of 4 operating modes by setting the timer x operating mode bits of the timer x mode register. (1) timer mode prescaler x counts the count source selected by the timer x count source selection bits. each time the count clock is input, the con- tents of prescaler x is decremented by 1. when the contents of prescaler x reach ?0 16 ? an underflow occurs at the next count clock, and the prescaler x latch is reloaded into prescaler x and count continues. the division ratio of prescaler x is 1/(n+1) pro- vided that the value of prescaler x is n. the contents of timer x is decremented by 1 each time the under- flow signal of prescaler x is input. when the contents of timer x reach ?0 16 ? an underflow occurs at the next count clock, and the timer x latch is reloaded into timer x and count continues. the di- vision ratio of timer x is 1/(m+1) provided that the value of timer x is m. accordingly, the division ratio of prescaler x and timer x is 1/((n+1) ? (m+1)) provided that the value of prescaler x is n and the value of timer x is m. (2) pulse output mode in the pulse output mode, the waveform whose polarity is inverted each time timer x underflows is output from the cntr 0 pin. the output level of cntr 0 pin can be selected by the cntr 0 ac- tive edge switch bit. when the cntr 0 active edge switch bit is ?? the output of cntr 0 pin is started at ??level. when this bit is ?? the output is started at ??level. also, the inverted waveform of pulse output from cntr 0 pin can be output from tx out pin by setting ??to the p0 3 /tx out output valid bit. when using a timer in this mode, set the port p1 4 a nd p0 3 d irec- tion registers to output mode. (3) event counter mode the timer a counts signals input from the p1 4 /cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. the active edge of cntr 0 pin input signal can be selected from rising or falling by the cntr 0 active edge switch bit .
7542 group rev.3.03 jul 11, 2008 page 32 of 117 rej03b0006-0303 (4) pulse width measurement mode in the pulse width measurement mode, the pulse width of the sig- nal input to p1 4 /cntr 0 pin is measured. the operation of timer x can be controlled by the level of the sig- nal input from the cntr 0 pin. when the cntr 0 active edge switch bit is ?? the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is ?? the count is stopped while the pin is ?? also, when the cntr 0 active edge switch bit is ?? the signal selected by the timer x count source selection bit is counted while the input signal level of cntr 0 pin is ?? the count is stopped while the pin is ?? t imer x can stop counting by setting ??to the timer x count stop bit in any mode. also, when timer x underflows, the timer x interrupt request bit is set to ?? note on timer x is described below; note on timer x (1) cntr 0 interrupt active edge selection-1 cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the rising edge of cntr 0 pin input signal. (2) cntr 0 interrupt active edge selection-2 according to the setting value of cntr 0 active edge switch bit, the interrupt request bit may be set to ?? when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the active edge switch bit. ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). fig. 29 structure of timer x mode register fig. 30 timer count source set register t i m e r x m o d e r e g i s t e r ( t x m : a d d r e s s 0 0 2 b 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : i n t e r r u p t a t f a l l i n g e d g e c o u n t a t r i s i n g e d g e ( i n e v e n t c o u n t e r m o d e ) 1 : i n t e r r u p t a t r i s i n g e d g e c o u n t a t f a l l i n g e d g e ( i n e v e n t c o u n t e r m o d e ) t i m e r x o p e r a t i n g m o d e b i t s b 1 b 0 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e n o t u s e d ( r e t u r n 0 w h e n r e a d ) t i m e r x c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 7 b 0 p 0 3 / t x o u t o u t p u t v a l i d b i t 0 : o u t p u t i n v a l i d ( i / o p o r t ) 1 : o u t p u t v a l i d ( i n v e r t e d c n t r 0 o u t p u t ) b7 b0 timer x count source selection bits b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) ( note 1 ) 1 1 : not available notes 1: f(x in ) can be used as timer x count source when using a ceramic resonator or on-chip oscillator. do not use it at rc oscillation. 2: on-chip oscillator can be used when the on-chip oscillator is enabled by bit 3 of cpum. timer count source set register (tcss : address 002a 16 , initial value: 00 16 ) timer b count source selection bits b7 b6 b5 0 0 0 : f(x in )/16 0 0 1 : f(x in )/2 0 1 0 : f(x in )/32 0 1 1 : f(x in )/64 1 0 0 : f(x in )/128 1 0 1 : f(x in )/256 1 1 0 : timer a underflow 1 1 1 : not available timer a count source selection bits b4 b3 b2 0 0 0 : f(x in )/16 0 0 1 : f(x in )/2 0 1 0 : f(x in )/32 0 1 1 : f(x in )/64 1 0 0 : f(x in )/128 1 0 1 : f(x in )/256 1 1 0 : on-chip oscillator output ( note 2 ) 1 1 1 : not available
7542 group rev.3.03 jul 11, 2008 page 33 of 117 rej03b0006-0303 fig. 31 block diagram of timer 1 and timer x q q p1 4 /cntr 0 r t 1/16 1/2 timer x interrupt request bit toggle flip-flop timer x count stop bit pulse width measurement mode event counter mode cntr 0 interrupt request bit pulse output mode port p1 4 latch port p1 4 direction register cntr 0 active edge switch bit timer mode pulse output mode cntr 0 active edge switch bit timer x count source selection bits 1/1 p0 3 /tx out prescaler x latch (8) prescaler x (8) timer x latch (8) timer x (8) data bus ? ? ? ? writing to timer x latch pulse output mode p0 3 /tx out output valid port p0 3 latch port p0 3 direction register prescaler 1 latch (8) prescaler 1 (8) timer 1 latch (8) timer 1 (8) 1/16 data bus timer 1 interrupt request frequency divider x in on-chip oscillator ?0 ?1 ?1 ? ?0 clock division ratio selection bits cpu mode register
7542 group rev.3.03 jul 11, 2008 page 34 of 117 rej03b0006-0303 tim er a,b t imer a and timer b are 16-bit timers and counts the signal which is the oscillation frequency selected by setting of the timer count source set register (tcss). timer a and timer b have the same function except of the count source clock selection. the count source clock of timer a is selected from among 1/2,1/ 16, 1/32, 1/64, 1/128, 1/256 of f(x in ) clock and on-chip oscillator clock. the count source clock of timer b is selected from among 1/2, 1/ 16, 1/32, 1/64, 1/128, 1/256 of f(x in ) clock and timer a underflow. t imer a (b) consists of the low-order of timer a: tal (timer b: tbl) and the high-order of timer a: tah (timer b: tbh). timer a (b) is decremented by 1 when each time of the count clock is in- put. when the contents of timer a (b) reach ?000 16 ? an underflow occurs at the next count clock, and the timer latch is re- loaded into timer. when timer a (b) underflows, the timer a (b) interrupt request bit is set to ?? t imer a (b) has the timer a (b) latch to retain the load value. the value of timer a (b) latch is set to timer a (b) at the timing of timer a (b) underflow. the division ratio of timer a (b) is 1/(n+1) pro- vided that the value of timer a (b) is n. when writing to both the low-order of timer a (b) and the high or- der of timer a (b) is executed, writing to ?atch only?or ?atch and timer?can be selected by the setting value of the timer a (b) write control bit. when reading from timer a (b) register is executed, the count value of timer a (b) is read out. be sure to write to/read out the low-order of timer a (b) and the high-order of timer a (b) in the following order; ?read read the high-order of timer a (b) first, and the low-order of timer a (b) next and be sure to read both high-order and low-order. ?write w rite to the low-order of timer a (b) first, and the high-order of t imer a (b) next and be sure to write both low-order and high or- der. t imer a and timer b can be used for the timing timer of input cap- ture and output compare function. notes on timer a, b (1) setting of timer value when ?: write to only latch?is set to the timer a (b) write control bit, written data to timer register is set to only latch even if timer is stopped. accordingly, in order to set the initial value for timer when it is stopped, set ?: write to latch and timer simultaneously?to timer a (b) write control bit. (2) read/write of timer a stop timer a to read/write its data when the system is in the follow- ing state; ?cpu operation clock source: x in oscillation ?timer a count source: on-chip oscillator output (3) read/write of timer b stop timer b to read/write its data when the system is in the fol- lowing state; ?cpu operation clock source: x in oscillation ?timer b count source: timer a underflow ?timer a count source: on-chip oscillator output
7542 group rev.3.03 jul 11, 2008 page 35 of 117 rej03b0006-0303 fig. 34 block diagram of timer a and timer b timer a (low-order) latch (8) timer a (low-order) (8) timer a (high-order) latch (8) timer a (high-order) (8) data bus timer a interrupt request compare capture timer b (low-order) latch (8) timer b (low-order) (8) timer b (high-order) latch (8) timer b (high-order) (8) data bus timer b interrupt request compare capture 1/2 1/16 1/32 1/64 1/128 1/256 timer a count stop bit timer a count source selection bits on-chip oscillator timer a write control bit timer b write control bit 1/2 1/16 1/32 1/64 1/128 1/256 timer b count stop bit timer b count source selection bits frequency divider on-chip oscillator x in ?0 ?1 ?1 clock division ratio selection bits ?0 frequency divider cpu mode register fig. 32 structure of timer a, b mode register fig. 33 timer count source set register t i m e r a , b m o d e r e g i s t e r ( t a b m : a d d r e s s 0 0 1 d 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 t i m e r a w r i t e c o n t r o l b i t 0 : w r i t e t o l a t c h a n d t i m e r s i m u l t a n e o u s l y 1 : w r i t e t o o n l y l a t c h t i m e r a c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r b w r i t e c o n t r o l b i t 0 : w r i t e t o l a t c h a n d t i m e r s i m u l t a n e o u s l y 1 : w r i t e t o o n l y l a t c h t i m e r b c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p n o t u s e d ( r e t u r n 0 w h e n r e a d ) c o m p a r e 0 , 1 m o d u l a t i o n m o d e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e 2 , 3 m o d u l a t i o n m o d e b i t 0 : d i s a b l e d 1 : e n a b l e d b7 b0 timer x count source selection bits b1 b0 0 0 : f(x in )/16 0 1 : f(x in )/2 1 0 : f(x in ) ( note 1 ) 1 1 : not available notes 1: f(x in ) can be used as timer x count source when using a ceramic resonator or on-chip oscillator. do not use it at rc oscillation. 2: on-chip oscillator can be used when the on-chip oscillator is enabled by bit 3 of cpum. timer count source set register (tcss : address 002a 16 , initial value: 00 16 ) timer b count source selection bits b7 b6 b5 0 0 0 : f(x in )/16 0 0 1 : f(x in )/2 0 1 0 : f(x in )/32 0 1 1 : f(x in )/64 1 0 0 : f(x in )/128 1 0 1 : f(x in )/256 1 1 0 : timer a underflow 1 1 1 : not available timer a count source selection bits b4 b3 b2 0 0 0 : f(x in )/16 0 0 1 : f(x in )/2 0 1 0 : f(x in )/32 0 1 1 : f(x in )/64 1 0 0 : f(x in )/128 1 0 1 : f(x in )/256 1 1 0 : on-chip oscillator output ( note 2 ) 1 1 1 : not available
7542 group rev.3.03 jul 11, 2008 page 36 of 117 rej03b0006-0303 output compare 7542 group has 4-output compare channels. each channel (0 to 3) has the same function and can be used to output waveform by us- ing count value of either timer a or timer b. the source timer for each channel is selected by setting value of the compare x (x = 0, 1, 2, 3) timer source bit. timer a and timer b can be selected for the source timer to each channel, respectively. to use each compare channel, set ??to the compare x output port bit and set the port direction register corresponding to com- pare channel to output mode. the compare value for each channel is set to the compare regis- ter (low-order) and compare register (high-order). w riting to the register for each channel is controlled by setting value of compare register write pointer. writing to each register is in the following order; 1.set the value of corresponded output compare channel to the compare register write pointer. 2.write a value to the compare register (low-order) and compare register (high-order). 3.set ??to the compare latch y (y = 00, 01, 10, 11, 20, 21, 30, 31) re-load bit. when ??is set to the compare latch y re-load bit, the value set to the compare register is loaded to compare latch when the next timer underflow. when count value of timer and setting value of compare latch is matched, compare output trigger occurs. when ?: enabled?is set to the compare trigger x enable bit, the output waveform from port is inverted by compare trigger. when ?: disabled?is set to the compare trigger x enable bit, the out- put waveform is not inverted, so port output can be fixed to ??or ?? when ?: positive?is set to the compare x output level latch, the compare output waveform is turned to ? level?at compare latch x0s match and turned to ? level?at compare latch x1s match. when ? :negative?is set to the compare x output level latch, the compare output waveform is turned to ? level?at compare latch x0s match and turned to ? level?at compare latch x1s match. the compare output level of each channel can be confirmed by reading the compare x output status bit. compare output interrupt is available when match of each com- pare channel and timer count value. the interrupt request from each channel can be disabled or enabled by setting value of com- pare latch y interrupt source bit. compare 0,1 (2,3) modulation mode in compare modulation mode, modulation waveform can be gener- ated by using compare channel 0 and 1, or compare channel 2 and 3. to use this mode, ?set ?: enabled?to the compare 0,1 (2, 3) modulation mode bit. ?set timer a underflow for timer b count source. ?set timer a for the timer source of compare channel 0 (2). ?set timer b for the timer source of compare channel 1 (3). in this mode, and waveform of compare 0 (1) and compare 2 (3) is generated from port p0 1 and p3 1 , respectively. accordingly, in order to use this mode, set ??to the compare 0 output port bit or compare 2 output port bit. fig. 35 structure of capture/compare register r/w pointer fig. 36 structure of compare register re-load register b 7 b 0 c o m p a r e r e g i s t e r r / w p o i n t e r b 2 b 1 b 0 000 : c o m p a r e l a t c h 0 0 001 : c o m p a r e l a t c h 0 1 010 : c o m p a r e l a t c h 1 0 011 : c o m p a r e l a t c h 1 1 100 : c o m p a r e l a t c h 2 0 101 : c o m p a r e l a t c h 2 1 110 : c o m p a r e l a t c h 3 0 111 : c o m p a r e l a t c h 3 1 n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e r e g i s t e r 0 r / w p o i n t e r 0 : c a p t u r e l a t c h 0 0 1 : c a p t u r e l a t c h 0 1 c a p t u r e r e g i s t e r 1 r / w p o i n t e r 0 : c a p t u r e l a t c h 1 0 1 : c a p t u r e l a t c h 1 1 n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e / c o m p a r e r e g i s t e r r / w p o i n t e r ( c c r p : a d d r e s s 0 0 1 2 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c o m p a r e l a t c h 0 0 , 0 1 r e - l o a d b i t 0 : r e - l o a d d i s a b l e d 1 : r e - l o a d a t n e x t u n d e r f l o w c o m p a r e l a t c h 1 0 , 1 1 r e - l o a d b i t 0 : r e - l o a d d i s a b l e d 1 : r e - l o a d a t n e x t u n d e r f l o w c o m p a r e l a t c h 2 0 , 2 1 r e - l o a d b i t 0 : r e - l o a d d i s a b l e d 1 : r e - l o a d a t n e x t u n d e r f l o w c o m p a r e l a t c h 3 0 , 3 1 r e - l o a d b i t 0 : r e - l o a d d i s a b l e d 1 : r e - l o a d a t n e x t u n d e r f l o w n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c o m p a r e r e g i s t e r r e - l o a d r e g i s t e r ( c m p r : a d d r e s s 0 0 1 4 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) notes on output compare ?when the selected source timer of each compare channel is stopped, written data to compare register is loaded to the com- pare latch simultaneously. ?do not write the same data to both of compare latch x0 and x1. ?when setting value of the compare latch is larger than timer set- ting value, compare match signal is not generated. accordingly, the output waveform is fixed to ??or ??level. however, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. accordingly, compare match interrupt occurs. ?when the compare x trigger enable bit is cleared to ??(dis- abled), the match trigger to the waveform output circuit is disabled, and the output waveform can be fixed to ??or ? level. however, in this case, the compare match signal is generated. accordingly, compare match interrupt occurs.
7542 group rev.3.03 jul 11, 2008 page 37 of 117 rej03b0006-0303 fig. 38 structure of timer source selection register fig. 39 structure of compare output mode register fig. 40 structure of capture/compare status register fig. 41 structure of compare interrupt source register b 7 b 0 c o m p a r e 0 t i m e r s o u r c e b i t c o m p a r e 1 t i m e r s o u r c e b i t c o m p a r e 2 t i m e r s o u r c e b i t c o m p a r e 3 t i m e r s o u r c e b i t c a p t u r e 0 t i m e r s o u r c e b i t c a p t u r e 1 t i m e r s o u r c e b i t n o t u s e d ( r e t u r n s 0 w h e n r e a d ) 0 : t i m e r a 1 : t i m e r b t i m e r s o u r c e s e l e c t i o n r e g i s t e r ( t m s r : a d d r e s s 0 0 1 f 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c o m p a r e 0 o u t p u t l e v e l l a t c h 0 : p o s i t i v e 1 : n e g a t i v e c o m p a r e 1 o u t p u t l e v e l l a t c h 0 : p o s i t i v e 1 : n e g a t i v e c o m p a r e 2 o u t p u t l e v e l l a t c h 0 : p o s i t i v e 1 : n e g a t i v e c o m p a r e 3 o u t p u t l e v e l l a t c h 0 : p o s i t i v e 1 : n e g a t i v e c o m p a r e 0 t r i g g e r e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e 1 t r i g g e r e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e 2 t r i g g e r e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e 3 t r i g g e r e n a b l e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e o u t p u t m o d e r e g i s t e r ( c m o m : a d d r e s s 0 0 2 1 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c o m p a r e 0 o u t p u t s t a t u s b i t 0 : l l e v e l o u t p u t 1 : h l e v e l o u t p u t c o m p a r e 1 o u t p u t s t a t u s b i t 0 : l l e v e l o u t p u t 1 : h l e v e l o u t p u t c o m p a r e 2 o u t p u t s t a t u s b i t 0 : l l e v e l o u t p u t 1 : h l e v e l o u t p u t c o m p a r e 3 o u t p u t s t a t u s b i t 0 : l l e v e l o u t p u t 1 : h l e v e l o u t p u t c a p t u r e 0 s t a t u s b i t 0 : l a t c h 0 0 c a p t u r e d 1 : l a t c h 0 1 c a p t u r e d c a p t u r e 1 s t a t u s b i t 0 : l a t c h 1 0 c a p t u r e d 1 : l a t c h 1 1 c a p t u r e d n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e / c o m p a r e s t a t u s r e g i s t e r ( c c s r : a d d r e s s 0 0 2 2 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c o m p a r e l a t c h 0 0 i n t e r r u p t s o u r c e b i t c o m p a r e l a t c h 0 1 i n t e r r u p t s o u r c e b i t c o m p a r e l a t c h 1 0 i n t e r r u p t s o u r c e b i t c o m p a r e l a t c h 1 1 i n t e r r u p t s o u r c e b i t c o m p a r e l a t c h 2 0 i n t e r r u p t s o u r c e b i t c o m p a r e l a t c h 2 1 i n t e r r u p t s o u r c e b i t c o m p a r e l a t c h 3 0 i n t e r r u p t s o u r c e b i t c o m p a r e l a t c h 3 1 i n t e r r u p t s o u r c e b i t 0 : d i s a b l e d 1 : e n a b l e d c o m p a r e i n t e r r u p t s o u r c e s e t r e g i s t e r ( c i s r : a d d r e s s 0 0 2 3 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) fig. 37 structure of capture/compare port register b 7 b 0 c a p t u r e 0 i n p u t p o r t b i t s b 1 b 0 00 : c a p t u r e f r o m p 0 0 01 : c a p t u r e f r o m p 1 0 10 : r i n g / 5 1 2 11 : n o t a v a i l a b l e c o m p a r e 0 o u t p u t p o r t b i t 0 : p 0 1 i s i / o p o r t 1 : p 0 1 i s c o m p a r e 0 c o m p a r e 1 o u t p u t p o r t b i t 0 : p 0 2 i s i / o p o r t 1 : p 0 2 i s c o m p a r e 1 c a p t u r e 1 i n p u t p o r t b i t 0 : c a p t u r e f r o m p 3 0 1 : r i n g / 5 1 2 c o m p a r e 2 o u t p u t p o r t b i t 0 : p 3 1 i s i / o p o r t 1 : p 3 1 i s c o m p a r e 2 c o m p a r e 3 o u t p u t p o r t b i t 0 : p 3 2 i s i / o p o r t 1 : p 3 2 i s c o m p a r e 3 n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e / c o m p a r e p o r t r e g i s t e r ( c c p r : a d d r e s s 0 0 1 e 1 6 , i n i t i a l v a l u e : 0 0 1 6 )
7542 group rev.3.03 jul 11, 2008 page 38 of 117 rej03b0006-0303 fig. 42 block diagram of output compare fig. 43 block diagram of compare channel 0 timer a latch timer a counter timer b counter timer b latch compare latch 00 compare latch 01 wave latch channel 0 compare 0 timer source bit compare channel 0 compare channel 1 compare channel 2 compare channel 3 p0 1 /cmp 0 p0 2 /cmp 1 p3 1 /cmp 2 p3 2 /cmp 3 compare buffer 00 (16) compare latch 00 (16) compare buffer 01 (16) compare latch 01 (16) data bus compare interrupt compare register write pointer (0012 16 , bits 0 to 2) compare latch 00, 01 re-load bit (0014 16 , bit 0) timer a counter (16) compare 0 timer source bit (001f 16 , bit 0) compare 0 trigger enable bit (0021 16 , bit 4) output latch compare 0 output level latch (0021 16 , bit 0) compare 0 output status bit (0022 16 , bit 0) compare 0 output port bit (001e 16 , bit 2) p0 1 /cmp 0 timer b counter (16) i/o port compare latch 00 interrupt source bit (0023 16 , bit 0) compare latch 01 interrupt source bit (0023 16 , bit 1) compare register
7542 group rev.3.03 jul 11, 2008 page 39 of 117 rej03b0006-0303 fig. 44 block diagram at modulation mode compare buffer 00 (16) compare latch 00 (16) compare buffer 01 (16) compare latch 01 (16) data bus compare register compare register write pointer (0012 16 , bits 0 to 2) compare latch 00, 01 re-load bit (0014 16 , bit 0) timer a counter (16) compare 0 (1) timer source bits (001f 16 , bit 0 (bit 1) compare 0 trigger enable bit (0021 16 , bit 4) output latch compare 0 output level latch (0021 16 , bit 0) compare 0 output status bit (0022 16 , bit 0) compare 0 output port bit (001e 16 , bit 2) p0 1 /cmp 0 timer b counter (16) compare 1 trigger enable bit (0021 16 , bit 5) output latch compare 1 output level latch (0021 16 , bit 1) compare 1 output status bit (0022 16 , bit 1) underflow compare latch 10 (16) compare buffer 10 (16) compare latch 11 (16) compare buffer 11 (16) data bus compare register compare latch 10, 11 re-load bit (0014 16 , bit 1) compare register write pointer (0012 16 , bits 0 to 2) i/o port
7542 group rev.3.03 jul 11, 2008 page 40 of 117 rej03b0006-0303 fig. 45 output compare mode (general waveform) fig. 46 output compare mode (compare register write timing) 000c 000b 000a 0009 0008 0007 0006 0005 0004 0003 0002 0001 000f 000e 000d 000c 000b 0000 000b 0005 0 1 0 timer underflow timer count value compare latch 00 compare latch 01 compare 00 match compare 01 match compare output compare interrupt compare status bit timer count clock note: compare interrupt occurs only for the interrupt source selected by compare interrupt source register. re-load the count value 000c 000b 000a 0009 0008 0007 0006 0005 0004 0003 0002 0001 000f 000e 000d 000c 000b 0000 000b 0005 0 1 1 0 000e 000c 0 timer underflow timer count value compare latch 00 compare latch 01 compare latch 00 write compare latch 01 write compare latch 00, 01 re-load bit compare latch 00, 01 re-load signal compare 00 match compare 01 match compare output compare interrupt compare status bit timer count clock re-load the count value
7542 group rev.3.03 jul 11, 2008 page 41 of 117 rej03b0006-0303 fig. 47 output compare mode (compare 0, 1 modulation mode) 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0007 0006 0005 0004 0003 0000 0006 0002 0 1 1 0 1 0004 0003 0002 0001 0000 0007 0006 0005 0004 0003 0002 0001 0007 0006 0005 0004 0003 0000 0004 0001 0 1 1 0 1 0 timer a underflow timer a count value compare latch 00 compare latch 01 compare 00 match compare 01 match compare 0 output compare 0 output status bit timer a count clock carrier wave generated by compare 0 compare 0 output timer b count value compare latch 10 compare latch 11 compare 10 match compare 11 match compare 1 output compare interrupt compare 1 output status bit timer a underflow modulation of output waveform generated by compare 1 modulation output note: compare interrupt occurs only for the interrupt source selected by compare interrupt source register. po rt outptu wavefowm
7542 group rev.3.03 jul 11, 2008 page 42 of 117 rej03b0006-0303 fig. 48 output compare mode (compare 0, 1 modulation mode: effect of output level latch) modulation output compare 1 output compare 0 output 1. when compare 0 output level latch is ?ositive? compare 1 output level latch is ?ositive? modulation output compare 1 output compare 0 output 2. when compare 0 output level latch is ?egative? compare 1 output level latch is ?ositive? modulation output compare 1 output compare 0 output 3. when compare 0 output level latch is ?ositive? compare 1 output level latch is ?egative? modulation output compare 1 output compare 0 output 4. when compare 0 output level latch is ?egative? compare 1 output level latch is ?egative?
7542 group rev.3.03 jul 11, 2008 page 43 of 117 rej03b0006-0303 input capture 7542 group has 2-input capture channels. each channel (0 and 1) has the same function and can be used to capture count value of either timer a or timer b. the source timer for each channel is selected by setting value of the capture x (x = 0, 1) timer source bit. timer a and timer b can be selected for the source timer to each channel, respectively. to use each capture channel, set the capture x input port bits and set the port direction register corresponding to capture channel to input mode. the input capture circuit retains the count value of selected timer when external trigger is input. the timer count value is retained to the capture latch x0 when rising edge is input and is retained to the capture latch x1 when falling edge is input. the count value of timer can be retained by software by capture y (y = 00, 01, 10, 11) software trigger bit too. when ??is set to this bit, count value of timer is retained to the corresponded capture latch. when reading from the capture y software trigger bit is executed, ??is read out. the latest status of capture latch can be confirmed by reading of the capture x status bit. this bit indicates the capture latch which latest data is in. the valid trigger edge for capture interrupt is set by the capture x interrupt edge selection bits. (regardless of the setting value of capture x interrupt edge selection bits, timer count values for both edges are retained to the capture latch.) each capture input has the noise filter circuit that judges continu- ous 4-time same level with sampling clock to be valid. the sampling clock of noise filter is set by the capture x noise filter clock selection bits. reading from the register for each channel is controlled by setting value of the capture register read pointer. reading from each reg- ister is in the following order; 1.set the value of the corresponded input capture channel to the capture register read pointer. 2.read from the capture register (low-order) and capture register (high-order). notes on input capture ?if the capture trigger is input while the capture register (low-order and high-order) is in read, captured value is changed between high-order reading and low-order reading. accordingly, some countermeasure by software is recommended, for example comparing the values that twice of read. ?when the on-chip-oscillator is selected for timer a count source, t imer a cannot be used for the capture source timer. t imer b cannot be used for the capture source timer when the system is in the following state; ?cpu operation clock source: x in oscillation ?timer b count source: timer a underflow ?timer a count source: on-chip oscillator output ?when writing ??to capture latch x0 (x1) software trigger bit of capture latch x0 and x1 at the same time, or external trigger and software trigger occur simultaneously, the set value of capture x status bit is undefined. ?when setting the interrupt active edge selection bit and noise fil- ter clock selection bit of external interrupt cap 0 , cap 1 , the interrupt request bit may be set to ?? when not requiring the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to ??(disabled). ? set the interrupt edge selection bit or noise filter clock selection bit. ? set the corresponding interrupt request bit to ??after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to ??(enabled). ?when the capture interrupt is used as the interrupt for return from stop mode, set the capture x noise filter clock selection bits to ?0 (filter stop)?
7542 group rev.3.03 jul 11, 2008 page 44 of 117 rej03b0006-0303 fig. 49 structure of capture software trigger register b 7 b 0 c a p t u r e r e g i s t e r 0 ( l o w - o r d e r ) ( c a p 0 l : a d d r e s s 0 0 0 c 1 6 ) b 7 b 0 c a p t u r e r e g i s t e r 0 ( h i g h - o r d e r ) ( c a p 0 h : a d d r e s s 0 0 0 d 1 6 ) b7 b0 c a p t u r e r e g i s t e r 1 ( l o w - o r d e r ) ( c a p 1 l : a d d r e s s 0 0 0 e 1 6 ) b 7 b 0 c a p t u r e r e g i s t e r 1 ( h i g h - o r d e r ) ( c a p 1 h : a d d r e s s 0 0 0 f 1 6 ) b 7 b 0 c a p t u r e 0 i n t e r r u p t e d g e s e l e c t i o n b i t s b 1 b 0 00 : r i s i n g a n d f a l l i n g e d g e 01 : r i s i n g e d g e 10 : f a l l i n g e d g e 11 : n o t a v a i l a b l e c a p t u r e 1 i n t e r r u p t e d g e s e l e c t i o n b i t s b 3 b 2 00 : r i s i n g a n d f a l l i n g e d g e 01 : r i s i n g e d g e 10 : f a l l i n g e d g e 11 : n o t a v a i l a b l e c a p t u r e 0 n o i s e f i l t e r c l o c k s e l e c t i o n b i t s b 5 b 4 00 : f i l t e r s t o p 01 : f ( x i n ) 10 : f ( x i n ) / 8 11 : f ( x i n ) / 3 2 c a p t u r e 1 n o i s e f i l t e r c l o c k s e l e c t i o n b i t s b 7 b 6 00 : f i l t e r s t o p 01 : f ( x i n ) 10 : f ( x i n ) / 8 11 : f ( x i n ) / 3 2 c a p t u r e m o d e r e g i s t e r ( c a p m : a d d r e s s 0 0 2 0 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) b 7 b 0 c a p t u r e l a t c h 0 0 s o f t w a r e t r i g g e r b i t c a p t u r e l a t c h 0 1 s o f t w a r e t r i g g e r b i t c a p t u r e l a t c h 1 0 s o f t w a r e t r i g g e r b i t c a p t u r e l a t c h 1 1 s o f t w a r e t r i g g e r b i t e a c h so f t w a r e t r i g g e r o c c u r s b y s e t t i n g 1 t o c o r r e s p o n d i n g b i t . ( r e t u r n s 0 w h e n r e a d ) n o t u s e d ( r e t u r n s 0 w h e n r e a d ) c a p t u r e s o f t w a r e t r i g g e r r e g i s t e r ( c s t r : a d d r e s s 0 0 1 3 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) fig. 50 structure of capture software trigger register/capture mode register
7542 group rev.3.03 jul 11, 2008 page 45 of 117 rej03b0006-0303 fig. 51 block diagram of input capture fig. 52 block diagram of capture channel 0 p1 0 /cap 0 p0 0 /cap 0 timer a latch timer a counter timer b counter timer b latch capture latch 00 capture latch 01 trigger input channel 0 capture 0 timer source bit capture channel 0 capture channel 1 ring /512 ring /512 p3 0 /cap 1 capture pointer (0013 16 , bits 4, 5) capture latch 00 (16) capture latch 01 (16) data bus capture interrupt capture register 0 read pointer (0012 16 , bit 4) timer a counter (16) capture 0 timer source bit (001f 16 , bit 4) capture trigger capture 0 status bit (0022 16 , bit 4) digital filter ring/512 capture latch 00 software trigger bit (0013 16 , bit 0) capture 0 input port bits (001e 16 , bits 0, 1) timer b counter (16) capture 0 interrupt edge selection bits (0020 16 , bits 0, 1) p1 0 /cap 0 capture register capture latch 0 (16) capture 0 noise filter clock selection bits (0020 16 , bits 4, 5) p0 0 /cap 0 rising falling
7542 group rev.3.03 jul 11, 2008 page 46 of 117 rej03b0006-0303 fig. 53 capture interrupt edge selection = ?ising edge fig. 54 capture interrupt edge selection = ?ising and falling edge 000c 000b 000a 0009 0008 0007 0006 0005 0004 0003 0002 0001 000f 000e 000d 000c 000b 0000 xxxx 000a 000c xxxx 0005 0001 000f 1 0 1 010 timer underflow capture input wave timer count value capture latch 00 capture latch 01 capture interrupt capture x (x=0, 1) status bit re-load the timer count value overwrite 000c 000b 000a 0009 0008 0007 0006 0005 0004 0003 0002 0001 000f 000e 000d 000c 000b 0000 1 0 1 010 xxxx 000a 000c xxxx 0005 0001 000f timer underflow capture input wave timer count value capture latch 00 capture latch 01 capture interrupt capture x (x=0, 1) status bit re-load the timer count value overwrite
7542 group rev.3.03 jul 11, 2008 page 47 of 117 rej03b0006-0303 fig. 55 block diagram of clock synchronous serial i/o1 fig. 56 operation of clock synchronous serial i/o1 function serial interface the 7542 group has serial i/o1 and serial i/o2. except that serial i/o1 has the bus collision detection function and the t x d 2 output structure for serial i/o2 is cmos only, they have the same function. serial i/o1 serial i/o1 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o1 mode clock synchronous serial i/o1 mode can be selected by setting the serial i/o1 mode selection bit of the serial i/o1 control register (bit 6) to ?? for clock synchronous serial i/o1, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. 1 / 4 1 / 4 f / f p 1 2 / s c l k 1 s e r i a l i / o 1 s t a t u s r e g i s t e r serial i/o1 control register p 1 3 / s r d y 1 p 1 0 / r x d 1 / c a p 0 p 1 1 / t x d 1 x in receive buffer register 1 a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r 1 r e c e i v e b u f f e r f u l l f l a g ( r b f ) re ceive interrupt request (ri) clo ck control circui t s h i f t c l o c k serial i/o1 synchronous clock selection bit frequency division ratio 1/(n+1) baud rate generator 1 address 001c 16 brg count source selection bit c l o c k c o n t r o l c i r c u i t falling-edge detector t r a n s m i t b u f f e r r e g i s t e r 1 data bus a d d r e s s 0 0 1 8 1 6 shift cloc k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) transmit interrupt source selection bit address 0019 16 data bus a d d r e s s 0 0 1 a 1 6 transmit shift register 1 d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd 1 serial input rxd 1 write pulse to receive/transmit buffer register 1 (address 0018 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd 1 pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. receive enable signal s rdy1
7542 group rev.3.03 jul 11, 2008 page 48 of 117 rej03b0006-0303 fig. 57 block diagram of uart serial i/o1 (2) asynchronous serial i/o1 (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o1 mode selection bit of the serial i/o1 control register to ?? eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 58 operation of uart serial i/o1 function x i n 1/4 oe pe fe 1/16 1 / 1 6 d a t a b u s r e c e i v e b u f f e r r e g i s t e r 1 a d d r e s s 0 0 1 8 1 6 r e c e i v e s h i f t r e g i s t e r 1 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) baud rate generator 1 f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) a d d r e s s 0 0 1 c 1 6 s t / s p / p a g e n e r a t o r transmit buffer register 1 data bus t r a n s m i t s h i f t r e g i s t e r 1 addr ess 0018 16 transmit shift completion flag (tsc) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) addr ess 0019 16 st detector sp detector u a r t 1 c o n t r o l r e g i s t e r address 001b 16 ch aracter length selection bit a d d r e s s 0 0 1 a 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t transmit interrupt source selection bit s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t c h a r a c t e r l e n g t h s e l e c t i o n b i t 7 b i t s 8 b i t s s e r i a l i / o 1 c o n t r o l r e g i s t e r p 1 2 / s c l k 1 serial i/o1 status register p 1 0 / r x d 1 / c a p 0 p1 1 /t x d 1 tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer 1 write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?,? can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the serial i/o1 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ? ? serial output t x d 1 serial input r x d 1 receive buffer 1 read signal
7542 group rev.3.03 jul 11, 2008 page 49 of 117 rej03b0006-0303 [transmit buffer register 1/receive buffer register 1 (tb1/ rb1)] 0018 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is ?? [serial i/o1 status register (sio1sts)] 0019 16 the read-only serial i/o1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o1 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to ??when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing ??to the serial i/o1 enable bit sioe (bit 7 of the serial i/o1 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o1 status register are initialized to ??at reset, but if the transmit enable bit of the serial i/o1 control regis- ter has been set to ?? the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become ?? [serial i/o1 control register (sio1con)] 001a 16 the serial i/o1 control register consists of eight control bits for the serial i/o1 function. [uart1 control register (uart1con)] 001b 16 the uart1 control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the p1 1 /txd 1 pin. [baud rate generator 1 (brg1)] 001c 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o1 ?serial i/o interrupt when setting the transmit enable bit to ?? the serial i/o transmit interrupt request bit is automatically set to ?? when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to ??(disabled). ? set the transmit enable bit to ?? ? set the serial i/o transmit interrupt request bit to ??after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to ??(enabled). ?i/o pin function when serial i/o1 is enabled. the functions of p1 2 and p1 3 are switched with the setting values of a serial i/o1 mode selection bit and a serial i/o1 synchronous clock selection bit as follows. (1) serial i/o1 mode selection bit ??: clock synchronous type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit ??: p1 2 pin turns into an output pin of a synchronous clock. ??: p1 2 pin turns into an input pin of a synchronous clock. setup of a s rdy1 output enable bit (srdy) ??: p1 3 pin can be used as a normal i/o pin. ??: p1 3 pin turns into a s rdy1 output pin. (2) serial i/o1 mode selection bit ??: clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o1 synchronous clock selection bit ?? p1 2 pin can be used as a normal i/o pin. ?? p1 2 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p1 3 pin. it can be used as a normal i/o pin.
7542 group rev.3.03 jul 11, 2008 page 50 of 117 rej03b0006-0303 fig. 59 structure of serial i/o1-related registers t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) b 7 b 7 s e r i a l i / o 1 s t a t u s r e g i s t e r s e r i a l i / o 1 c o n t r o l r e g i s t e r b 0 b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) 1 : f ( x i n ) / 4 s e r i a l i / o 1 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 1 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 1 3 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 1 3 p i n o p e r a t e s a s s r d y 1 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 1 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 1 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o 1 d i s a b l e d ( p i n s p 1 0 t o p 1 3 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 1 e n a b l e d ( p i n s p 1 0 t o p 1 3 o p e r a t e a s s e r i a l i / o p i n s ) b7 u a r t 1 c o n t r o l r e g i s t e r c haracter length selection bit (chas) 0: 8 bits 1: 7 bits pa rity enable bit (pare) 0: parity checking disabled 1: parity checking enabled parity selection bit (pars) 0: even parity 1: odd parity st op bit length selection bit (stps) 0: 1 stop bit 1: 2 stop bits p1 1 /t x d 1 p- ch annel output disable bit (poff) 0: cmos output (in output mode) 1: n-channel open drain output (in output mode) not us ed (return ??when read) b0 ( s i o 1 s t s : a d d r e s s 0 0 1 9 1 6 , i n i t i a l v a l u e : 8 0 1 6 ) ( s i o 1 c o n : a d d r e s s 0 0 1 a 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) ( u a r t 1 c o n : a d d r e s s 0 0 1 b 1 6 , i n i t i a l v a l u e : e 0 1 6 )
7542 group rev.3.03 jul 11, 2008 page 51 of 117 rej03b0006-0303 bus collision detection (sio1) sio1 can detect a bus collision by setting uart1 bus collision de- tection interrupt enable bit. when transmission is started in the clock synchronous or asyn- chronous (uart) serial i/o mode, the transmit pin txd 1 is compared with the receive pin rxd 1 in synchronization with rising edge of transmit shift clock. if they do not coincide with each other, a bus collision detection interrupt request occurs. when a transmit data collision is detected between lsb and msb of transmit data in the clock synchronous serial i/o mode or be- tween the start bit and stop bit of transmit data in uart mode, a bus collision detection can be performed by both the internal clock and the external clock. a block diagram is shown in fig. 61. a timing diagram is shown in fig. 62. note: bus collision detection can be used when sio1 is operating at full-duplex communication. when sio1 is operating at half-duplex communication, set bus collision detection inter- rupt to be disabled. fig. 61 block diagram of bus collision detection interrupt circuit fig. 62 timing diagram of bus collision detection interrupt d txd 1 rxd 1 shift clock ua r t1 bus collision detection interrupt valid bit (address 000a 16 , bit 1) ua r t1 bus collision detection interrupt discrimination bit (address 000b 16 , bit 1) ke y-on wakeup/ ua r t1 bus collision detection interrupt request bit (address 003c 16 , bit 6) ke y-on wakeup interrupt request q 0 : no interrupt request issued interrupt source set register (intset: address 000a 16 , initial value: 00 16 ) key-on wakeup interrupt valid bit b7 b0 0: interrupt invalid interrupt source discrimination register (intdis: address 000b 16 , initial value: 00 16 ) key-on wakeup interrupt discrimination bit b7 b0 interrupt request register 1 (ireq1 : address 003c 16 , initial value : 00 16 ) serial i/o1 receive interrupt request bit b7 b0 serial i/o1 receive interrupt enable bit 0 : interrupts disabled interrupt control register 1 (icon1 : address 003e 16 , initial value : 00 16 ) b7 b0 1 : interrupts enabled cntr 0 interrupt enable bit key-on wake up/uart1 bus collision int 1 interrupt enable bit int 0 interrupt enable bit serial i/o2 transmit interrupt enable bit serial i/o2 receive interrupt enable bit serial i/o1 transmit interrupt enable bit detection interrupt enable bit 1 : interrupt request issued cntr 0 interrupt request bit detection interrupt request bit key-on wake up/uart1 bus collision int 1 interrupt request bit int 0 interrupt request bit serial i/o2 transmit interrupt request bit serial i/o2 receive interrupt request bit serial i/o1 transmit interrupt request bit 1: interrupt occurs 0: interrupt does not occur not used (returns ??when read) timer 1 interrupt discrimination bit a/d conversion interrupt discrimination bit discrimination bit uart1 bus collision detection interrupt 1: interrupt valid not used (returns ??when read) timer 1 interrupt valid bit a/d conversion interrupt valid bit uart1 bus collision detection interrupt valid bit fig. 60 bus collision detection circuit related registers bus collision detection interrupt generation data collision tr ansmit shift clock tr ansmit pin txd 1 receive pin rxd 1
7542 group rev.3.03 jul 11, 2008 page 52 of 117 rej03b0006-0303 fig. 63 block diagram of clock synchronous serial i/o2 fig. 64 operation of clock synchronous serial i/o2 function serial i/o2 serial i/o2 can be used as either clock synchronous or asynchro- nous (uart) serial i/o. a dedicated timer is also provided for baud rate generation. (1) clock synchronous serial i/o2 mode clock synchronous serial i/o2 mode can be selected by setting the serial i/o2 mode selection bit of the serial i/o2 control register (bit 6) to ?? for clock synchronous serial i/o2, the transmitter and the receiver must use the same clock. if an internal clock is used, transfer is started by a write signal to the tb/rb. d 7 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 0 d 1 d 2 d 3 d 4 d 5 d 6 rbf = 1 tsc = 1 tbe = 0 tbe = 1 tsc = 0 transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) serial output txd 2 serial input rxd 2 write pulse to receive/transmit buffer register 2 (address 002e 16 ) overrun error (oe) detection notes 1: as the transmit interrupt (ti), which can be selected, either when the transmit buffer has emptied (tbe=1) or after the transmit shift operation has ended (tsc=1), by setting the transmit interrupt source selection bit (tic) of the serial i/o2 control register. 2: if data is written to the transmit buffer register when tsc=0, the transmit clock is generated continuously and serial data is output continuously from the txd 2 pin. 3: the receive interrupt (ri) is set when the receive buffer full flag (rbf) becomes ??. receive enable signal s rdy2 1 / 4 1 / 4 f / f p 0 6 / s c l k 2 s e r i a l i / o 2 s t a t u s r e g i s t e r s e r i a l i / o 2 c o n t r o l r e g i s t e r p 0 7 / s r d y 2 p 0 4 / r x d 2 p 0 5 / t x d 2 x i n r e c e i v e b u f f e r r e g i s t e r 2 a d d r e s s 0 0 2 e 1 6 r e c e i v e s h i f t r e g i s t e r 2 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e i n t e r r u p t r e q u e s t ( r i ) c l o c k c o n t r o l c i r c u i t s h i f t c l o c k s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t f r e q u e n c y d i v i s i o n r a t i o 1 / ( n + 1 ) b a u d r a t e g e n e r a t o r 2 a d d r e s s 0 0 3 2 1 6 b r g c o u n t s o u r c e s e l e c t i o n b i t c l o c k c o n t r o l c i r c u i t f a l l i n g - e d g e d e t e c t o r t r a n s m i t b u f f e r r e g i s t e r 2 d a t a b u s a d d r e s s 0 0 2 e 1 6 s h i f t c l o c k t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) t r a n s m i t i n t e r r u p t r e q u e s t ( t i ) t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t a d d r e s s 0 0 2 f 1 6 d a t a b u s a d d r e s s 0 0 3 0 1 6 t r a n s m i t s h i f t r e g i s t e r 2
7542 group rev.3.03 jul 11, 2008 page 53 of 117 rej03b0006-0303 fig. 65 block diagram of uart serial i/o2 (2) asynchronous serial i/o2 (uart) mode clock asynchronous serial i/o mode (uart) can be selected by clearing the serial i/o2 mode selection bit of the serial i/o2 control register to ?? eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. fig. 66 operation of uart serial i/o2 function x in 1/4 oe pe fe 1/16 1/16 data bus receive buffer register 2 address 002e 16 receive shift register 2 receive buffer full flag (rbf) receive interrupt request (ri) baud rate generator 2 frequency division ratio 1/(n+1) address 0032 16 st/sp/pa generator transmit buffer register 2 data bus transmit shift register 2 address 002e 16 transmit shift completion flag (tsc) transmit buffer empty flag (tbe) transmit interrupt request (ti) address 002f 16 st detector sp detector uart2 control register address 0031 16 character length selection bit address 0030 16 brg count source selection bit transmit interrupt source selection bit serial i/o2 synchronous clock selection bit clock control circuit character length selection bit 7 bits 8 bits serial i/o2 control register p0 6 /s clk2 serial i/o2 status register p0 4 /r x d 2 p0 5 /t x d 2 tsc=0 tbe=1 rbf=0 tbe=0 tbe=0 rbf=1 rbf=1 st d 0 d 1 sp d 0 d 1 st sp tbe=1 tsc=1 st d 0 d 1 sp d 0 d 1 st sp transmit or receive clock transmit buffer 2 write signal generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: error flag detection occurs at the same time that the rbf flag becomes ??(at 1st stop bit, during reception). 2: as the transmit interrupt (ti), when either the tbe or tsc flag becomes ?,? can be selected to occur depending on the settin g of the transmit interrupt source selection bit (tic) of the serial i/o2 control register. 3: the receive interrupt (ri) is set when the rbf flag becomes ?. 4: after data is written to the transmit buffer when tsc=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to tsc=0. notes ? ? serial output t x d 2 serial input r x d 2 receive buffer 2 read signal
7542 group rev.3.03 jul 11, 2008 page 54 of 117 rej03b0006-0303 [transmit buffer register 2/receive buffer register 2 (tb2/ rb2)] 002e 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer is write-only and the receive buffer is read-only. if a character bit length is 7 bits, the msb of data stored in the receive buffer is ?? [serial i/o2 status register (sio2sts)] 002f 16 the read-only serial i/o2 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial i/o2 function and various errors. three of the flags (bits 4 to 6) are valid only in uart mode. the receive buffer full flag (bit 1) is cleared to ??when the receive buffer register is read. if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. a write to the serial i/o1 status register clears all the error flags oe, pe, fe, and se (bit 3 to bit 6, respectively). writing ??to the serial i/o2 enable bit sioe (bit 7 of the serial i/o2 control register) also clears all the status flags, including the error flags. bits 0 to 6 of the serial i/o2 status register are initialized to ??at reset, but if the transmit enable bit of the serial i/o2 control regis- ter has been set to ?? the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become ?? [serial i/o2 control register (sio2con)] 0030 16 the serial i/o2 control register consists of eight control bits for the serial i/o2 function. [uart2 control register (uart2con)] 0031 16 the uart control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial i/o is selected and set the data format of an data transfer. [baud rate generator 2 (brg2)] 0032 16 the baud rate generator determines the baud rate for serial transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. notes on serial i/o2 ?serial i/o interrupt when setting the transmit enable bit to ?? the serial i/o transmit interrupt request bit is automatically set to ?? when not requiring the interrupt occurrence synchronized with the transmission en- abled, take the following sequence. ? set the serial i/o transmit interrupt enable bit to ??(disabled). ? set the transmit enable bit to ?? ? set the serial i/o transmit interrupt request bit to ??after 1 or more instructions have been executed. ? set the serial i/o transmit interrupt enable bit to ??(enabled). ?i/o pin function when serial i/o2 is enabled. the functions of p0 6 and p0 7 are switched with the setting values of a serial i/o2 mode selection bit and a serial i/o2 synchronous clock selection bit as follows. (1) serial i/o2 mode selection bit ??: clock synchronous type serial i/o is selected. setup of a serial i/o2 synchronous clock selection bit ??: p0 6 pin turns into an output pin of a synchronous clock. ??: p0 6 pin turns into an input pin of a synchronous clock. setup of a s rdy2 output enable bit (srdy) ??: p0 7 pin can be used as a normal i/o pin. ??: p0 7 pin turns into a s rdy2 output pin. (2) serial i/o2 mode selection bit ??: clock asynchronous (uart) type serial i/o is selected. setup of a serial i/o2 synchronous clock selection bit ?? p0 6 pin can be used as a normal i/o pin. ?? p0 6 pin turns into an input pin of an external clock. when clock asynchronous (uart) type serial i/o is selected, it is p0 7 pin. it can be used as a normal i/o pin.
7542 group rev.3.03 jul 11, 2008 page 55 of 117 rej03b0006-0303 t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l t r a n s m i t s h i f t c o m p l e t i o n f l a g ( t s c ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d o v e r r u n e r r o r f l a g ( o e ) 0 : n o e r r o r 1 : o v e r r u n e r r o r p a r i t y e r r o r f l a g ( p e ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e ) 0 : n o e r r o r 1 : f r a m i n g e r r o r s u m m i n g e r r o r f l a g ( s e ) 0 : ( o e ) u ( p e ) u ( f e ) = 0 1 : ( o e ) u ( p e ) u ( f e ) = 1 n o t u s e d ( r e t u r n s 1 w h e n r e a d ) b 7 b 7 s e r i a l i / o 2 s t a t u s r e g i s t e r s e r i a l i / o 2 c o n t r o l r e g i s t e r b 0 b 0 b r g c o u n t s o u r c e s e l e c t i o n b i t ( c s s ) 0 : f ( x i n ) 1 : f ( x i n ) / 4 s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t i o n b i t ( s c s ) 0 : b r g o u t p u t d i v i d e d b y 4 w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , b r g o u t p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . 1 : e x t e r n a l c l o c k i n p u t w h e n c l o c k s y n c h r o n o u s s e r i a l i / o i s s e l e c t e d , e x t e r n a l c l o c k i n p u t d i v i d e d b y 1 6 w h e n u a r t i s s e l e c t e d . s r d y 2 o u t p u t e n a b l e b i t ( s r d y ) 0 : p 0 7 p i n o p e r a t e s a s o r d i n a r y i / o p i n 1 : p 0 7 p i n o p e r a t e s a s s r d y 2 o u t p u t p i n t r a n s m i t i n t e r r u p t s o u r c e s e l e c t i o n b i t ( t i c ) 0 : i n t e r r u p t w h e n t r a n s m i t b u f f e r h a s e m p t i e d 1 : i n t e r r u p t w h e n t r a n s m i t s h i f t o p e r a t i o n i s c o m p l e t e d t r a n s m i t e n a b l e b i t ( t e ) 0 : t r a n s m i t d i s a b l e d 1 : t r a n s m i t e n a b l e d r e c e i v e e n a b l e b i t ( r e ) 0 : r e c e i v e d i s a b l e d 1 : r e c e i v e e n a b l e d s e r i a l i / o 2 m o d e s e l e c t i o n b i t ( s i o m ) 0 : c l o c k a s y n c h r o n o u s ( u a r t ) s e r i a l i / o 1 : c l o c k s y n c h r o n o u s s e r i a l i / o s e r i a l i / o 2 e n a b l e b i t ( s i o e ) 0 : s e r i a l i / o 2 d i s a b l e d ( p i n s p 0 4 t o p 0 7 o p e r a t e a s o r d i n a r y i / o p i n s ) 1 : s e r i a l i / o 2 e n a b l e d ( p i n s p 0 4 t o p 0 7 o p e r a t e a s s e r i a l i / o p i n s ) b 7 u a r t 2 c o n t r o l r e g i s t e r c h a r a c t e r l e n g t h s e l e c t i o n b i t ( c h a s ) 0 : 8 b i t s 1 : 7 b i t s p a r i t y e n a b l e b i t ( p a r e ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d p a r i t y s e l e c t i o n b i t ( p a r s ) 0 : e v e n p a r i t y 1 : o d d p a r i t y s t o p b i t l e n g t h s e l e c t i o n b i t ( s t p s ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s n o t u s e d ( r e t u r n 0 w h e n r e a d ) ( d o n o t w r i t e 1 t o t h i s b i t . ) n o t u s e d ( r e t u r n 1 w h e n r e a d ) b 0 ( s i o 2 s t s : a d d r e s s 0 0 2 f 1 6 , i n i t i a l v a l u e : 8 0 1 6 ) ( s i o 2 c o n : a d d r e s s 0 0 3 0 1 6 , i n i t i a l v a l u e : 0 0 1 6 ) (uart2con : address 0031 16 , in itial value: e0 16 ) fig. 67 structure of serial i/o2-related registers
7542 group rev.3.03 jul 11, 2008 page 56 of 117 rej03b0006-0303 a/d converter the functional blocks of the a/d converter are described below. [a/d conversion register] ad the a/d conversion register is a read-only register that stores the result of a/d conversion. do not read out this register during an a/ d conversion. [a/d control register] adcon the a/d control register controls the a/d converter. bit 2 to 0 are analog input pin selection bits. bit 3 is the a/d conversion clock selection bit. when ??is set to this bit, the a/d conversion clock is f(x in )/2 and the a/d conversion time is 122 cycles of f(x in ). when ??is set to this bit, the a/d conversion clock is f(x in ) and the a/d conversion time is 61 cycles of f(x in ). bit 4 is the a/d conversion completion bit. the value of this bit re- mains at ??during a/d conversion, and changes to ??at completion of a/d conversion. a/d conversion is started by setting this bit to ?? [comparison voltage generator] the comparison voltage generator divides the voltage between av ss and v ref by 1024, and outputs the divided voltages. [channel selector] the channel selector selects one of ports p2 7 /an 7 to p2 0 /an 0 , and inputs the voltage to the comparator. [comparator and control circuit] the comparator and control circuit compares an analog input volt- age with the comparison voltage and stores its result into the a/d conversion register. when a/d conversion is completed, the con- trol circuit sets the a/d conversion completion bit and the a/d interrupt request bit to ?? because the comparator is constructed linked to a capacitor, set f(x in ) in order that the a/d conversion clock is 250 khz or over during a/d conversion. notes on a/d converter as for ad translation accuracy, on the following operating condi- tions, accuracy may become low. (1) since the analog circuit inside a microcomputer becomes sen- sitive to noise when v ref voltage is set up lower than vcc voltage, accuracy may become low rather than the case where v ref voltage and vcc voltage are set up to the same value.. (2) when v ref voltage is lower than [ 3.0 v ], the accuracy at the low temperature may become extremely low compared with that at room temperature. when the system would be used at low temperature, the use at v ref =3.0 v or more is recom- mended. fig. 68 structure of a/d control register fig. 69 structure of a/d conversion register read 8-bit (read only address 0035 16 ) b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 (address 0035 16 ) read 10-bit (read in order address 0036 16 , 0035 16 ) b7 b0 b9 b8 (address 0036 16 ) b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 (address 0035 16 ) note: high-order 6-bit of address 0036 16 returns ??when read. not used (returns ??when read) a/d conversion completion bit 0 : conversion in progress 1 : conversion completed b7 b0 analog input pin selection bits 000 : p2 0 /an 0 001 : p2 1 /an 1 010 : p2 2 /an 2 011 : p2 3 /an 3 100 : p2 4 /an 4 101 : p2 5 /an 5 110 : p2 6 /an 6 (note 1) 111 : p2 7 /an 7 (note 1) notes 1: these can be used only for 36 pin version. 2: a/d conversion clock=f(x in ) can be used only when ceramic oscillation or on-chip oscillator is used. select f(x in )/2 when rc oscillation is used. a/d control register (adcon : address 0034 16 , initial value: 10 16 ) a/d conversion clock selection bit (note 2) 0 : f(x in )/2 1 : f(x in )
7542 group rev.3.03 jul 11, 2008 page 57 of 117 rej03b0006-0303 fig. 70 block diagram of a/d converter a/d control register (address 0034 16 ) channel selector a/d control circuit resistor ladder v ref comparator a/d interrupt request b7 b0 data bus 3 10 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 p2 6 /an 6 p2 7 /an 7 a/d conversion register (low-order) (address 0036 16 ) (address 0035 16 ) a/d conversion register (high-order) v ss f(x in ) f(x in )/2
7542 group rev.3.03 jul 11, 2008 page 58 of 117 rej03b0006-0303 w atchdog timer the watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. the watchdog timer consists of an 8-bit watchdog timer h and an 8-bit watchdog timer l, being a 16-bit counter. standard operation of watchdog timer the watchdog timer stops when the watchdog timer control regis- ter (address 0039 16 ) is not set after reset. writing an optional value to the watchdog timer control register (address 0039 16 ) causes the watchdog timer to start to count down. when the watchdog timer h underflows, an internal reset occurs. accord- ingly, it is programmed that the watchdog timer control register (address 0039 16 ) can be set before an underflow occurs. when the watchdog timer control register (address 0039 16 ) is read, the values of the high-order 6-bit of the watchdog timer h, stp instruction function selection bit and watchdog timer h count source selection bit are read. initial value of watchdog timer by a reset or writing to the watchdog timer control register (ad- dress 0039 16 ), the watchdog timer h is set to ?f 16 ?and the watchdog timer l is set to ?f 16 ? operation of watchdog timer h count source selection bit a watchdog timer h count source can be selected by bit 7 of the watchdog timer control register (address 0039 16 ). when this bit is ?? the count source becomes a watchdog timer l underflow sig- nal. the detection time is 131.072 ms at f(x in )=8 mhz. when this bit is ?? the count source becomes f(x in )/16. in this case, the detection time is 512 s at f(x in )=8 mhz. this bit is cleared to ??after reset. operation of stp instruction function selection bit when ??is set to stp instruction function selection bit, system enters into the stop mode at the stp instruction execution. when ??is set to this bit, internal reset occurs at the stp instruc- tion execution. this bit is set to ??by program, but it cannot be changed to ??. this bit is cleared to ??after reset. notes on watchdog timer 1. the watchdog timer is operating during the wait mode. write data to the watchdog timer control register to prevent timer underflow. 2. the watchdog timer stops during the stop mode. however, the watchdog timer is running during the oscillation stabilizing time after the stp instruction is released. in order to avoid the under- flow of the watchdog timer, the watchdog timer control register must be written just before executing the stp instruction. 3. the stp instruction function selection bit (bit 6 of watchdog timer control register (address 0039 16 )) can be rewritten only once after releasing reset. after rewriting it is disable to write any data to this bit. 4. a count source of watchdog timer is affected by the clock divi- sion selection bit of the cpu mode register. the f(x in ) clock is supplied to the watchdog timer when select- ing f(x in ) as the cpu clock. the on-chip oscillator output is supplied to the watchdog timer when selecting the on-chip oscillator output as the cpu clock. fig. 71 block diagram of watchdog timer fig. 72 structure of watchdog timer control register watchdog timer control register (wdtcon: address 0039 16 , initial value: 3f 16 ) watchdog timer h (read only for high-order 6-bit) stp instruction function selection bit 0 : system enters into the stop mode at the stp instruction execution 1 : internal reset occurs at the stp instruction execution watchdog timer h count source selection bit 0 : watchdog timer l underflow 1 : f(x in )/16 or on-chip oscillator/16 b7 b0 xin clock on-chip oscillator source clock selection (auto-switch depending on setting of cpum) data bus ? ? 1/16 watchdog timer h count source selection bit reset circuit stp instruction function selection bit watchdog timer h (8) write "ff 16 " to the watchdog timer control register internal reset reset watchdog timer l (8) stp instruction write ?f 16 ?to the watchdog timer control register
7542 group rev.3.03 jul 11, 2008 page 59 of 117 rej03b0006-0303 reset circuit the 7542 group starts operation by the on-chip oscillator after sys- tem is released from reset. accordingly, when the rising of power supply voltage passes 2.2v, set the reset input voltage to become below 0.2vcc (0.44v). moreover, switch cpu clock to the external oscillator after the ris- ing of power supply voltage passes the minimum operation voltage and after an oscillation is stabilized. note: the minimum operation voltage is decided by the division ratio of an external oscillator's frequency and a cpu clock. decide on an external oscillator's oscillation stabilizing time after fully evaluating an oscillator's stabilizing time used. fig. 73 example of reset circuit fig. 74 timing diagram at reset (note) 0.2 v cc 0 v 0 v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage vcc = 2.2 v data address 8-13 clock cycles reset address from the vector table 1 : an on-chip oscillator applies about ring? mhz, ?50 khz frequency clock at average of vcc = 5 v. 2 : the mark ??means that the address is changeable depending on the previous state. 3 : these are all internal signals except reset. notes ?? fffc fffd ad h ,ad l ??? ?? ad l ad h ??? clock from on-chip oscillator ring reset reset out sync
7542 group rev.3.03 jul 11, 2008 page 60 of 117 rej03b0006-0303 fig. 75 internal status of microcomputer at reset prescaler 1 (pre1) timer 1 (t1) timer x mode register (txm) prescaler x (prex) timer x (tx) timer count source set register (tcss) serial i/o2 status register (sio2sts) a/d control register (adcon) misrg watchdog timer control register (wdtcon) interrupt edge selection register (intedge) cpu mode register (cpum) interrupt request register 1 (ireq1) interrupt control register 1 (icon1) (18) (19) (20) (21) (22) (23) (29) (30) (31) (32) (33) (34) ff 16 01 16 00 16 00 16 ff 16 ff 16 00 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002f 16 0030 16 0034 16 0037 16 0039 16 003a 16 003b 16 003c 16 003e 16 0011 1111 00 16 00 16 00 16 1000 0000 processor status register program counter contents of address fffc 16 (pc h ) (pc l ) (ps) notes 1: x : undefined 2: the content of other registers is undefined when the microcomputer is reset. the initial values must be surely set before you use it. 3: only flash memory version has this register. contents of address fffd 16 xxxx x1xx port p0 direction register (p0d) port p1 direction register (p1d) port p2 direction register (p2d) port p3 direction register (p3d) pull-up control register (pull) (1) (2) (3) (4) (13) register contents 00 16 00 16 00 16 00 16 0001 16 0003 16 0005 16 0007 16 0016 16 serial i/o1 control register (sio1con) uart1 control register (uart1con) (16) (17) serial i/o1 status register (sio1sts) (15) 001a 16 001b 16 00 16 1110 0000 0019 16 1000 0000 xxx 0 0000 address port p1p3 control register (p1p3c) (14) 0017 16 00 16 timer a, b mode register (tabm) capture/compare port register (ccpr) timer source selection register (tmsr) 00 16 00 16 00 16 001d 16 001e 16 001f 16 00 16 00 16 00 16 0020 16 0021 16 0022 16 00 16 0023 16 (35) (36) (37) (38) (39) (41) (42) (43) (44) (45) serial i/o2 control register (sio2con) 0031 16 interrupt request register 2 (ireq2) 003d 16 00 16 interrupt control register 2 (icon2) 003f 16 00 16 (46) (47) (48) (49) uart2 control register (uart2con) on-chip oscillation division ratio selection register (rodr) 00 16 0038 16 (40) 0000 0010 0001 0000 1110 0000 1000 0000 capture mode register (capm) compare output mode register (cmom) (25) (26) (27) (28) ff 16 0024 16 ff 16 ff 16 0025 16 0026 16 0027 16 ff 16 timer a (low-order) (tal) timer a (high-order) (tah) timer b (low-order) (tbl) timer b (high-order) (tbh) (24) capture/compare status register (ccsr) compare interrupt source register (cisr) (8) (9) (10) (11) (12) interrupt source discrimination register (intdis) compare register (low-order) (cmpl) (6) (7) interrupt source set register (intset) (5) 000b 16 0010 16 00 16 000a 16 compare register (high-order) (cmph) capture/compare register r/w pointer (ccrp) capture software trigger register (cstr) 00 16 00 16 00 16 0011 16 0012 16 0013 16 00 16 00 16 0014 16 0015 16 compare register re-load register (cmpr) port p0p3 drive capacity control register (dccr) 00 16 00 16 (51) (52) flash memory control register 0 (fmcr0) (note 3) flash memory control register 1 (fmcr1) (note 3) 0fe0 16 0fe1 16 0000 0001 01 00 0000 (50) flash memory control register 2 (fmcr2) (note 3) 0fe2 16 00 00 0001
7542 group rev.3.03 jul 11, 2008 page 61 of 117 rej03b0006-0303 fig. 77 external circuit of ceramic resonator fig. 78 external circuit of rc oscillation fig. 79 external clock input circuit fig. 76 processing of x in and x out pins at on-chip oscillator operation clock generating circuit an oscillation circuit can be formed by connecting a resonator be- tween x in and x out , and an rc oscillation circuit can be formed by connecting a resistor and a capacitor. use the circuit constants in accordance with the resonator manufacturer's recommended values. no external resistor is needed between x in and x out since a feed-back resistor exists on-chip. (an external feed-back resistor may be needed depending on conditions.) (1) on-chip oscillator operation when the mcu operates by the on-chip oscillator for the main clock, connect x in pin to v cc through a resistor and leave x out pin open. the clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. be careful that variable frequencies when designing application products. (2) ceramic resonator when the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. a feedback resistor is built in be- tween pins x in and x out . (3) rc oscillation when the rc oscillation is used for the main clock, connect the x in pin and x out pin to the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. (4) external clock when the external signal clock is used for the main clock, connect the x in pin to the clock source and leave x out pin open. select ??(ceramic oscillation) to oscillation mode selection bit of cpu mode register (003b 16 ). insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. also, if the oscillator manufacturers data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feed- back resistor between x in and x out following the instruction. note: connect the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is af- fected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. note: the clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. be careful that variable frequencies and obtain the sufficient margin. note: x in x out external oscillation circuit v c c v ss o p e n m37542 x i n x o u t c r m 3 7 5 4 2 x in c o u t c i n x out m 3 7 5 4 2 r d x i n x o u t m 3 7 5 4 2 o p e n r
7542 group rev.3.03 jul 11, 2008 page 62 of 117 rej03b0006-0303 (1) oscillation control ?stop mode when the stp instruction is executed, the internal clock stops at an ??level and the x in oscillator stops. at this time, timer 1 is set to ?1 16 ?and prescaler 1 is set to ?f 16 ?when the oscillation sta- bilization time set bit after release of the stp instruction is ?? on the other hand, timer 1 and prescaler 1 are not set when the above bit is ?? accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. f(x in )/16 is forcibly connected to the input of prescaler 1. when an external interrupt is accepted, oscillation is restarted but the internal clock remains at ??until timer 1 underflows. as soon as timer 1 underflows, the internal clock is supplied. this is because when a ceramic oscil- lator is used, some time is required until a start of oscillation. in case oscillation is restarted by reset, no wait time is generated. so apply an ??level to the reset pin while oscillation becomes stable, or set the wait time by on-chip oscillator operation after system is released from reset until the oscillation is stabled. with the flash version, the internal power supply circuit is changed to low power consumption mode for consumption current reduction at the time of stp instruction execution. although an internal power supply circuit is usually changed to the normal operation mode at the time of the return from an stp in- struction, since a certain time is required to start the power supply to flash and operation of flash to be enabled, set wait time 100 s or more with the flash version by the oscillation stabiliza- tion time set function after release of the stp instruction which used the timer 1. ?wait mode if the wit instruction is executed, the internal clock stops at an ??level, but the oscillator does not stop. the internal clock re- starts if a reset occurs or when an interrupt is received. since the oscillator does not stop, normal operation can be started immedi- ately after the clock is restarted. to ensure that interrupts will be received to release the stp or wit state, interrupt enable bits must be set to ??before the stp or wit instruction is executed. notes on clock generating circuit for use with the oscillation stabilization set bit after release of the stp instruction set to ?? set values in timer 1 and prescaler 1 af- ter fully appreciating the oscillation stabilization time of the oscillator to be used. ?switch of ceramic and rc oscillations after releasing reset the operation starts by starting an on-chip os- cillator. then, a ceramic oscillation or an rc oscillation is selected by setting bit 5 of the cpu mode register. ?double-speed mode when a ceramic oscillation is selected, a double-speed mode can be used. do not use it when an rc oscillation is selected. fig. 80 structure of cpu mode register o s c i l l a t i o n m o d e s e l e c t i o n b i t ( n o t e 1 ) 0 : c e r a m i c o s c i l l a t i o n 1 : r c o s c i l l a t i o n c p u m o d e r e g i s t e r ( c p u m : a d d r e s s 0 0 3 b 1 6 , i n i t i a l v a l u e : 8 0 1 6 ) s t a c k p a g e s e l e c t i o n b i t 0 : 0 p a g e 1 : 1 p a g e c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b 7 b 6 0 0 : f ( ) = f ( x i n ) / 2 ( h i g h - s p e e d m o d e ) 0 1 : f ( ) = f ( x i n ) / 8 ( m i d d l e - s p e e d m o d e ) 1 0 : a p p l i e d f r o m on - c h i p o s c i l l a t o r 1 1 : f ( ) = f ( x i n ) ( d o u b l e - s p e e d m o d e ) ( n o t e 2 ) o n - c h i p o s c i l l a t o r o s c i l l a t i o n c o n t r o l b i t 0 : o n - c h i p o s c i l l a t o r o s c i l l a t i o n e n a b l e d 1 : o n - c h i p o s c i l l a t o r o s c i l l a t i o n s t o p x in o scillation control bit 0 : ceramic or rc oscillation enabled 1 : ceramic or rc oscillation stop p r o c e s s o r m o d e b i t s ( n o t e 1 ) b 1 b 0 0 0 s i n g l e - c h i p m o d e 0 1 1 0 1 1 n o t a v a i l a b l e b7 b0 2: t hese bits are used only when a ceramic oscillation is selected. note s 1: the bit can be rewritten only once afte r rel easing reset. after rewriting i t i s d i s a b l e t o w r i t e a n y d a t a t o t h e b i t . h o w e v e r , b y r e s e t t h e b i t i s i n i t i a l i z e d a n d c a n b e r e w r i t t e n , a g a i n . ( i t i s n o t d i s a b l e t o w r i t e a n y d a t a t o t h e b i t f o r e m u l a t o r m c u m 3 7 5 4 2 r s s . ) do not use these when an rc oscillation is selected. ?cpu mode register bits 5, 1 and 0 of cpu mode register are used to select oscillation mode and to control operation modes of the microcomputer. in or- der to prevent the dead-lock by error-writing (ex. program run-away), these bits can be rewritten only once after releasing re- set. after rewriting it is disable to write any data to the bit. (the emulator mcu ?37542rss?is excluded.) also, when the read-modify-write instructions (seb, clb) are ex- ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. ? clock division ratio, x in oscillation control, on-chip oscillator control the state transition shown in fig. 84 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 84. ? count source (timer 1, timer a, timer b, timer x, serial i/o, serial i/o2, a/d converter, watchdog timer) a count source of watchdog timer is affected by the clock divi- sion selection bit of the cpu mode register. the f(x in ) clock is supplied to the watchdog timer when select- ing f(x in ) as the cpu clock. the on-chip oscillator output is supplied to the watchdog timer when selecting the on-chip oscillator output as the cpu clock.
7542 group rev.3.03 jul 11, 2008 page 63 of 117 rej03b0006-0303 on-chip oscillation division ratio at on-chip oscillator mode, division ratio of on-chip oscillator for cpu clock is selected by setting value of on-chip oscillation divi- sion ratio selection register. the division ratio of on-chip oscillation for cpu clock is selected from among 1/1, 1/2, 1/8, 1/128. the op- eration clock for the peripheral function block is not changed by setting value of this register. notes on on-chip oscillation division ratio ?when system is released from reset, r osc /8 (on-chip oscillator middle-speed mode) is selected for cpu clock. ? when state transition from the ceramic or rc oscillation to on- chip oscillator, r osc /8 (on-chip oscillator middle-speed mode) is selected for cpu clock. ? when the mcu operates by on-chip oscillator for the main clock without external oscillation circuit, connect x in pin to v cc through a resistor and leave x out pin open. set ?0010x00 2 ?(x = 0 or 1) to cpum. fig. 81 structure of on-chip oscillation division ratio selection register on-chip oscillation division ratio selection register (rodr: address 0037 16 , initial value: 02 16 ) on-chip oscillator division ratio b1 b0 00 : on-chip oscillator double-speed mode (r osc /1) 01 : on-chip oscillator high-speed mode (r osc /2) 10 : on-chip oscillator middle-speed mode (r osc /8) 11 : on-chip oscillator low-speed mode (r osc /128) not used (returns ??when read) b7 b0
7542 group rev.3.03 jul 11, 2008 page 64 of 117 rej03b0006-0303 fig. 82 block diagram of internal clock generating circuit (for ceramic resonator) fig. 83 block diagram of internal clock generating circuit (for rc oscillation) s r q s r q 1/2 r s q (note) 1/4 1/2 wit instruction stp instruction timing (internal clock) stp instruction interrupt request reset interrupt disable flag l high-speed mode middle-speed mode prescaler 1 timer 1 clock division ratio selection bits double-speed mode on-chip oscillator mode on-chip oscillator x out x in 1/16 clock division ratio selection bits middle-, high-, double-speed mode on-chip oscillator mode 1/4 1/2 on-chip oscillator division ratio selection bits r osc /128 r osc /8 r osc /2 r osc /1 reset although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. note: s r q s r q 1/2 r s q 1/4 1/2 wit instruction stp instruction timing (internal clock) stp instruction interru p t re q uest reset interrupt disable flag l high-speed mode middle-speed mode prescaler 1 timer 1 clock division ratio selection bits double-speed mode ring x out x in delay clock division ratio selection bits middle-, high-, double-speed mode on-chip oscillator mode reset on-chip oscillator mode on-chip oscillator division ratio selection bits on-chip oscillator 1/16 1/4 1/2 r osc /128 r osc /8 r osc /2 r osc /1
7542 group rev.3.03 jul 11, 2008 page 65 of 117 rej03b0006-0303 fig. 84 state transition stp mode f(x in ) oscillation: stop on-chip oscillator: stop w ait mode 1 wa it mode 2 wa it mode 3 wa it mode 3 operation clock source: on-chip oscillator (note 2) operation clock source: f(x in ) (note 1) notes on switch of clock (1) in operation clock = f(x in ), the following can be selected for the cpu clock division ratio. f(x in )/2 (high-speed mode) f(x in )/8 (middle-speed mode) f(x in ) (double-speed mode, only at a ceramic oscillation) (2) in operation clock = on-chip oscillator, the following can be selected for the cpu clock division ratio. r osc /1 (on-chip oscillator double-speed mode) r osc /2 (on-chip oscillator high-speed mode) r osc /8 (on-chip oscillator middle-speed mode) r osc /128 (on-chip oscillator low-speed mode) (3) after system is released from reset, and state transition of state 2 state 3 and state transition of state 2 state 3? r osc /8 (on-chip oscillator middle-speed mode) is selected for cpu clock. (4) executing the state transition state 3 to 2 or state 3 to 3 after stabilizing x in oscillation. (5) when the state 2 state 3 state 4 is performed, execute the nop instruction as shown below according to the division ratio of cpu clock. 1. cpum 76 = 10 2 (state 2 state 3) 2. nop instruction tr ansition from double-speed mode: nop ? 3 tr ansition from high-speed mode: nop ? 1 tr ansition from middle-speed mode: nop ? 0 3. cpu 4 = 1 2 (state 3 state 4) (6) when the state 3 state 2 state 1 is performed, execute the nop instruction as shown below according to the division ratio of cpu clock. 1. cpum 76 = 00 2 or 01 2 or 11 2 (state 3 state 2) 2. nop instruction tr ansition from on-chip oscillator double-speed mode: nop ? 4 tr ansition from on-chip oscillator high-speed mode: nop ? 2 tr ansition from on-chip oscillator middle-speed mode: nop ? 0 tr ansition from on-chip oscillator low-speed mode: nop ? 0 3. cpum 3 = 1 2 (state 2 state 1) wa it mode 4 state 4 reset state f(x in ) oscillation: enabled on-chip oscillator: enabled state 3 state 3 wa it mode 2 state 2 state 2 state 1 interrupt stp instruction interrupt wit instruction interrupt cpum 3 =0 2 cpum 3 =1 2 cpum 76 =10 2 ( note 3 ) cpum 76 =00 2 01 2 11 2 ( note 4 ) cpum 76 =10 2 ( note 3 ) cpum 76 =00 2 01 2 11 2 misrg 1 =1 2 misrg 1 =0 2 misrg 1 =1 2 ( note 4 ) misrg 1 =0 2 reset released ( note 3 ) cpum 4 =0 2 cpum 4 =1 2 interrupt wit instruction wit instruction interrupt wit instruction interrupt wit instruction interrupt wit instruction stp instruction stp instruction stp instruction interrupt interrupt interrupt f(x in ) oscillation: enabled on-chip oscillator: stop f(x in ) oscillation: enabled on-chip oscillator: enabled f(x in ) oscillation: enabled on-chip oscillator: enabled f(x in ) oscillation: enabled on-chip oscillator: enabled f(x in ) oscillation: enabled on-chip oscillator: enabled oscillation stop detection circuit valid f(x in ) oscillation: stop on-chip oscillator: enabled
7542 group rev.3.03 jul 11, 2008 page 66 of 117 rej03b0006-0303 fig. 85 structure of misrg oscillation stop detection circuit the oscillation stop detection circuit is used to detect an oscilla- tion stop when a ceramic resonator or oscillation circuit stops due to disconnection. to use the oscillation stop detection circuit, set the on-chip oscillator to start operating. the oscillation stop detection circuit is enabled by setting the ce- ramic or rc oscillation stop detection function active bit to 1. while this circuit is enabled, the operating status of the ceramic or rc oscillation circuit is monitored using the on-chip oscillator. if an oscillation stop is detected, the oscillation stop detection status bit is set to 1. if the oscillation stop detection reset enable bit is also set to 1, an internal reset is triggered at oscillation stop detection. the ceramic or rc oscillation stop detection function active bit and the oscillation stop detection status bit are not initialized if an oscillation stop detection reset is triggered and these bits retain their value of 1. since these bits are initialized to 0 by an external reset, an oscillation stop detection reset can be determined by checking the oscillation stop status bit. the oscillation stop detection status bit is set to 0 by writing 0 to the ceramic or rc oscillation stop detection function active bit. to enable the oscillation detection circuit, first write 0 to the ce- ramic or rc oscillation stop detection function active bit and set the oscillation stop detection status bit to 0. then set the ceramic or rc oscillation stop detection function active bit to 1. the ceramic oscillation, rc oscillation, and external clock input are set as the clocks for oscillation stop detection. refer to the electrical characteristics for the frequencies for oscillation stop de- tection. notes on oscillation stop detection circuit (1) do not execute the transition to ?tate 2??shown in figure 86 state transition of oscillation stop detection circuit. in this state, no reset is triggered and the mcu is stopped even when the x in oscillation is stopped. (2) after an oscillation stop detection reset, if this reset is enabled while bits ceramic or rc oscillation stop detection function ac- tive and oscillation stop detection status are retained, a reset is triggered again. (3) the oscillation stop detection status bit is initialized under the following conditions: ?external reset, power-on reset, low-voltage detection reset, watchdog timer reset, and reset by the stp instruction func- tion. ?write 0 to the ceramic or rc oscillation stop detection func- tion active bit. (4) while the oscillation stop detection function is in active, the os- cillation stop detection status bit may set to 1 when the watchdog timer underflow. when an oscillation stop detection reset is triggered, reconfirm that oscillation is stopped. (5) the oscillation stop detection circuit is not included in the emu- lator mcu ?37542rss? misrg(address 0038 16 , initial value: 00 16 ) b7 b0 oscillation stabilization time set bit after release of the stp instruction 0: set ?1 16 ?in timer1, and ?f 16 in prescaler 1 automatically 1: not set automatically reserved bits ( d o n ot wri te ?? to t h ese b i ts) not used (return ??when read) oscillation stop detection status bit 0: oscillation stop not detected 1: oscillation stop detected oscillation stop reset bit 0: oscillation stop reset disabled 1: oscillation stop reset enabled ceramic or rc oscillation stop detection function active bit 0: detection function inactive 1: detection function active
7542 group rev.3.03 jul 11, 2008 page 67 of 117 rej03b0006-0303 fig. 86 state transition 2 operation clock source: on-chip oscillator (note 2) operation clock source: f(x in ) (note 1) notes on switch of clock (1) in operation clock = f(x in ), the following can be selected for the cpu clock division ratio. f(x in )/2 (high-speed mode) f(x in )/8 (middle-speed mode) f(x in ) (double-speed mode, only at a ceramic oscillation) (2) in operation clock = on-chip oscillator, the following can be selected for the cpu clock division ratio. r osc /1 (on-chip oscillator double-speed mode) r osc /2 (on-chip oscillator high-speed mode) r osc /8 (on-chip oscillator middle-speed mode) r osc /128 (on-chip oscillator low-speed mode) (3) executing the state transition state 3 to 2 or state 3 to 3 after stabilizing x in oscillation. (4) after system is released from reset, and state transition of state 2 state 3 and state transition of state 2 state 3? r osc /8 (on-chip oscillator middle-speed mode) is selected for cpu clock. (5) mcu cannot be returned by on-chip oscillator and its operation is stopped since internal reset does not occur at oscillati on stop detected. accordingly, do not execute the transition to state 2'a. (6) stp instruction cannot be used when oscillation stop detection circuit is in active. reset state 2 f(x in ) oscillation: enabled on-chip oscillator: enabled reset state 1 f(x in ) oscillation: enabled on-chip oscillator: enabled oscillation stop detection circuit is in active. (note 6) applied ??to reset pin (external reset) misrg 3 is cleared to ?? misrg 2 =1 2 misrg 2 =0 2 misrg 2 =1 2 misrg 2 =0 2 misrg 1 =1 2 misrg 1 =0 2 (misrg 3 is cleared to ??) misrg 1 =1 2 ( note 3 ) misrg 1 =0 2 (misrg 3 is cleared to ??) state 3 state 2 f(x in ) oscillation: enabled on-chip oscillator: enabled f(x in ) oscillation: enabled on-chip oscillator: enabled state 3 state 2 f(x in ) oscillation: enabled on-chip oscillator: enabled state 2? (note 5) oscillation stop reset disabled when oscillation stop is detected; misrg 3 is set to ?? internal reset does not occur. prohibitive state muc will be locked when ceramic or rc oscillation is stopped. state 3? oscillation stop reset disabled when oscillation stop is detected; misrg 3 is set to ?? internal reset does not occur. oscillation stop reset enabled when oscillation stop is detected; misrg 3 is set to ?? internal reset occurs. oscillation stop reset enabled when oscillation stop is detected; misrg 3 is set to ?? internal reset occurs. state 3? release from internal reset misrg 3 is set to ?? oscillation status can be confirmed by reading misrg 3 . f(x in ) oscillation: enabled on-chip oscillator: enabled state 3? state 2? cpum 76 =10 2 ( note 4 ) cpum 76 =00 2 01 2 11 2 ( note 3 ) cpum 76 =10 2 cpum 76 =00 2 01 2 11 2 cpum 76 =10 2 ( note 4 ) cpum 76 =00 2 01 2 11 2 reset released ( note 4 ) reset released ( note 4 ) oscillation stop is detected (internal reset)
7542 group rev.3.03 jul 11, 2008 page 68 of 117 rej03b0006-0303 notes on programming processor status register the contents of the processor status register (ps) after reset are undefined except for the interrupt disable flag i which is ?? after reset, initialize flags which affect program execution. in particular, it is essential to initialize the t flag and the d flag because of their effect on calculations. interrupts the contents of the interrupt request bit do not change even if the bbc or bbs instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. for executing the instruction for the changed contents, execute one instruction before executing the bbc or bbs instruction. decimal calculations ?for calculations in decimal notation, set the decimal mode flag d to ?? then execute the adc instruction or sbc instruction. in this case, execute sec instruction, clc instruction or cld in- struction after executing one instruction before the adc instruction or sbc instruction. ?in the decimal mode, the values of the n (negative), v (overflow) and z (zero) flags are invalid. ports ?the values of the port direction registers cannot be read. that is, it is impossible to use the lda instruction, memory opera- tion instruction when the t flag is ?? addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs. it is also impossible to use bit operation instructions such as clb and seb and read/modify/write instructions of direction registers for calculations such as ror. for setting direction registers, use the ldm instruction, sta in- struction, etc. a/d conversion do not execute the stp instruction during a/d conversion. instruction execution timing the instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles men- tioned in the machine-language instruction table. the frequency of the internal clock is the same as that of the x in in double-speed mode, twice the x in cycle in high-speed mode and 8 times the x in cycle in middle-speed mode. cpu mode register the oscillation mode selection bit and processor mode bits can be rewritten only once after releasing reset. however, after rewriting it is disable to write any value to the bit. (emulator mcu is ex- cluded.) when a ceramic oscillation is selected, a double-speed mode of the clock division ratio selection bits can be used. do not use it when an rc oscillation is selected. state transition do not stop the clock selected as the operation clock because of setting of cm3, 4. notes on hardware handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 f to 0.1 f is recommended. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1.mask rom order confirmation form * 2.mark specification form * for the mask rom confirmation and the mark specifications, refer to the "renesas technology corp." homepage (http://www.renesas.com/en/rom).
7542 group rev.3.03 jul 11, 2008 page 69 of 117 rej03b0006-0303 notes on use countermeasures against noise 1. shortest wiring length (1) package select the smallest possible package to make the total wiring length short. the wiring length depends on a microcomputer package. use of a small package, for example qfp and not dip, makes the total wir- ing length short to reduce influence of noise. (3) wiring for clock input/output pins ?make the length of wiring which is connected to clock i/o pins as short as possible. ?make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the v ss pin of a microcomputer as short as possible. ?separate the v ss pattern only for oscillation from other v ss pat- terns. if noise enters clock i/o pins, clock waveforms may be deformed. this may cause a program failure or program runaway. also, if a potential difference is caused by the noise between the v ss level of a microcomputer and the v ss level of an oscillator, the correct clock will not be input in the microcomputer. (2) wiring for reset pin make the length of wiring which is connected to the reset pin as short as possible. especially, connect a capacitor across the reset pin and the v ss pin with the shortest possible wiring (within 20mm). the width of a pulse input into the reset pin is determined by the timing necessary conditions. if noise having a shorter pulse width than the standard is input to the reset pin, the reset is released before the internal state of the microcomputer is completely initial- ized. this may cause a program runaway. fig. 89 wiring for clock i/o pins fig. 87 selection of packages dip sdip sop qfp fig. 88 wiring for the reset pin reset reset circuit noise v ss v ss reset circuit v ss reset v ss n.g. o.k. noise x in x out v ss x in x out v ss n.g. o.k. (4) wiring to cnvss pin connect the cnvss pin to the vss pin with the shortest possible wiring. in the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memory version, from the mcu by a jumper switch. the processor mode of a microcomputer is influenced by a poten- tial at the cnvss pin. if a potential difference is caused by the noise between pins cnvss and vss, the processor mode may be- come unstable. this may cause a microcomputer malfunction or a program runaway. a wiring of a serial rewrite circuit may function as an antenna which feeds noise into the microcomputer. fig. 90 wiring for cnvss pin n o i s e cnv ss v ss n . g . c n v s s v s s o.k. c n v s s v s s j u m p e r s w i t c h s e r i a l r e w r i t e c i r c u i t o . k . f l a s h m e m o r y v e r s i o n
7542 group rev.3.03 jul 11, 2008 page 70 of 117 rej03b0006-0303 fig. 91 bypass capacitor across the v ss line and the v cc line 2. connection of bypass capacitor across v ss line and v cc line connect an approximately 0.1 f bypass capacitor across the v ss line and the v cc line as follows: ?connect a bypass capacitor across the v ss pin and the v cc pin at equal length. ?connect a bypass capacitor across the v ss pin and the v cc pin with the shortest possible wiring. ?use lines with a larger diameter than other signal lines for v ss line and v cc line. ?connect the power source wiring via a bypass capacitor to the v ss pin and the v cc pin. v ss v cc v ss v cc n.g. o.k. 3. wiring to analog input pins ?connect an approximately 100 ? to 1 k ? resistor to an analog signal line which is connected to an analog input pin in series. besides, connect the resistor to the microcomputer as close as possible. ?connect an approximately 1000 pf capacitor across the vss pin and the analog input pin. besides, connect the capacitor to the vss pin as close as possible. also, connect the capacitor across the analog input pin and the vss pin at equal length. signals which is input in an analog input pin (such as an a/d con- verter/comparator input pin) are usually output signals from sensor. the sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. this long wiring func- tions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. fig. 92 analog signal line and a resistor and a capacitor analog input pin v ss noise thermistor microcomputer n.g. o.k. (note) note : the resistor is used for dividing resistance with a thermistor. ?the analog input pin is connected to the capacitor of a voltage comparator. accordingly, sufficient accuracy may not be ob- tained by the charge/discharge current at the time of a/d conversion when the analog signal source of high-impedance is connected to an analog input pin. in order to obtain the a/d con- version result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an ana- log input pin.
7542 group rev.3.03 jul 11, 2008 page 71 of 117 rej03b0006-0303 4. oscillator concerns t ake care to prevent an oscillator that generates clocks for a mi- crocomputer operation from being affected by other signals. (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows. in the system using a microcomputer, there are signal lines for controlling motors, leds, and thermal heads or others. when a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) installing oscillator away from signal lines where potential lev- els change frequently install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. signal lines where potential levels change frequently (such as the cntr pin signal line) may affect other lines at signal rising edge or falling edge. if such lines cross over a clock line, clock wave- forms may be deformed, which causes a microcomputer failure or a program runaway. ? keeping oscillator away from large current signal lines ? installing oscillator away from signal lines where potential lev- els change frequently fig. 93 wiring for a large current signal line/writing of signal lines where potential levels change frequently x i n x o u t v s s m microcomputer mutual inductance large curr ent gnd x in x out v s s cntr d o n o t c r o s s n.g. (3) oscillator protection using vss pattern as for a two-sided printed circuit board, print a vss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. connect the vss pattern to the microcomputer vss pin with the shortest possible wiring. besides, separate this vss pattern from other vss patterns. fig. 94 vss pattern on the underside of an oscillator x in x out v ss an example of v ss patterns on the underside of a printed circuit board oscillator wiring pattern example separate the v ss line for oscillation from other v ss lines
7542 group rev.3.03 jul 11, 2008 page 72 of 117 rej03b0006-0303 5. setup for i/o ports setup i/o ports using hardware and software as follows: ?connect a resistor of 100 ? or more to an i/o port in series. ?as for an input port, read data several times by a program for checking whether input levels are equal or not. ?as for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. ?rewrite data to direction registers and pull-up control registers at fixed periods. fig. 95 setup for i/o ports 6. providing of watchdog timer function by software if a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. this is equal to or more effective than program runaway detection by a hardware watchdog timer. the following shows an example of a watchdog timer provided by software. in the following example, to reset a microcomputer to normal op- eration, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. this example assumes that interrupt processing is repeated mul- tiple times in a single main routine processing. fig. 96 watchdog timer by software ?assigns a single byte of ram to a software watchdog timer (swdt) and writes the initial value n in the swdt once at each execution of the main routine. the initial value n should satisfy the following condition: n+1 (counts of interrupt processing executed in each main routine) as the main routine execution cycle may change because of an interrupt processing or others, the initial value n should have a margin. ?watches the operation of the interrupt processing routine by comparing the swdt contents with counts of interrupt process- ing after the initial value n has been set. ?detects that the interrupt processing routine has failed and de- termines to branch to the program initialization routine for recovery processing in the following case: if the swdt contents do not change after interrupt processing. ?decrements the swdt contents by 1 at each interrupt process- ing. ?determines that the main routine operates normally when the swdt contents are reset to the initial value n at almost fixed cycles (at the fixed interrupt processing count). ?detects that the main routine has failed and determines to branch to the program initialization routine for recovery process- ing in the following case: if the swdt contents are not initialized to the initial value n but continued to decrement and if they reach 0 or less. main routine (swdt) n cli main processing (swdt) interrupt processing routine errors n interrupt processing routine (swdt) (swdt)? interrupt processing (swdt) main routine errors > 0 0 rti return =n? 0? n direction register port latch data bus i/o port pins noise noise n.g. o.k.
7542 group rev.3.03 jul 11, 2008 page 73 of 117 rej03b0006-0303 t able 9 summary of 7542 groups flash memory version flash memory mode the 7542 groups flash memory version has the flash memory that can be rewritten with a single power source. for this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and the cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). summary t able 9 lists the summary of the 7542 group (flash memory ver- sion). this flash memory version has some blocks on the flash memory as shown in figure 97 and each block can be erased. in addition to the ordinary user rom area to store the mcu op- eration control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the users application sys- tem. this boot rom area can be rewritten in only parallel i/o mode. item power source voltage (vcc) te mperature at program/erase program/erase v pp voltage (v pp ) flash memory mode erase block division user rom area/data rom area boot rom area (note) program method erase method program/erase control method number of commands number of program/erase times rom code protection specifications v cc = 2.7 to 5.5 v ta = 0 to 60 ? v cc = 2.7 to 5.5 v 3 modes; parallel i/o mode, standard serial i/o mode, cpu rewrite mode refer to fig. 97. not divided (4k bytes) in units of bytes block erase program/erase control by software command 5 commands 100 a vailable in parallel i/o mode and standard serial i/o mode note : the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. this boot rom area can be erased and written in only parallel i/o mode.
7542 group rev.3.03 jul 11, 2008 page 74 of 117 rej03b0006-0303 fig. 97 block diagram of built-in flash memory boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the stan- dard serial i/o mode becomes unusable.) see figure 97 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset and the cnv ss pin high after pulling the p3 7 (rp) pin low, p3 2 (ce) pin high, p0 6 /s clk pin low and p0 5 /txd 2 pin high, the cpu starts operating (start address of program is stored into addresses fffc 16 and fffd 16 ) using the control program in the boot rom area. this mode is called the ?oot mode? also, user rom area can be rewritten using the con- trol program in the boot rom area. block address block addresses refer to the maximum address of each block. these addresses are used in the block erase command. notes 1: the boot rom area can be rewritten in a parallel i/o mode. (access to except boot rom area is disablrd.) 2: to specify a block, use the maximum address in the block. 3: the mask rom version has the reserved rom area. note the difference of the area. sfr area sfr area internal ram area (1k bytes) internal flash memory area (4k bytes) (note 3) internal flash memory area (32k bytes) (note 3) 0000 16 0040 16 043f 16 0fe0 16 ram 8000 16 0fff 16 ffff 16 7000 16 user rom area 7000 16 7800 16 8000 16 e000 16 c000 16 ffff 16 f000 16 ffff 16 32k bytes rom product data block b : 2k bytes boot rom area 4k bytes data block a : 2k bytes b lock 2 : 16k bytes b lock 1 : 8k bytes b lock 0 : 8k bytes sfr area sfr area internal ram area (1k bytes) internal flash memory area (4k bytes) (note 3) internal flash memory area (16k bytes) (note 3) 0000 16 0040 16 043f 16 0fe0 16 ram c000 16 0fff 16 7fff 16 ffff 16 7000 16 sfr area 7000 16 7800 16 7fff 16 e000 16 c000 16 ffff 16 16k bytes rom product data block b : 2k bytes data block a : 2k bytes b lock 1 : 8k bytes b lock 0 : 8k bytes cpu rewrite mode in cpu rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the central process- ing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 97 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite con- trol program must be transferred to internal ram area before it can be executed. ?outline performance cpu rewrite mode is usable in the single-chip or boot mode. the only user rom area can be rewritten. in cpu rewrite mode, the cpu erases, programs and reads the in- ternal flash memory as instructed by software commands. this rewrite control program must be transferred to internal ram area before it can be executed. the mcu enters cpu rewrite mode by setting ??to the cpu re- write mode select bit (bit 1 of address 0fe0 16 ). then, software commands can be accepted. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register.
7542 group rev.3.03 jul 11, 2008 page 75 of 117 rej03b0006-0303 fig. 98 structure of flash memory control register 0 b7 b0 flash memory control register 0 (fmcr0: address : 0fe0 16 : initial value: 01 16 ) ry/by status flag 0 : busy (being written or erased) 1 : ready cpu rewrite mode select bit (note 1) 0 : cpu rewrite mode invalid 1 : cpu rewrite mode valid 8kb user block e/w mode enable bit (note 1, 2) 0 : e/w disabled 1 : e/w enabled flash memory reset bit (note 3) 0 : normal operation 1 : reset not used (do not write ??to this bit.) user rom area select bit (note 4) 0 : boot rom area is accessed 1 : user rom area is accessed program status flag 0: pass 1: error erase status flag 0: pass 1: error notes 1: for this bit to be set to ?? the user needs to write a ??and then a ??to it in succession. for this bit to be set to ?? write ??only to this bit. 2: this bit can be written only when cpu rewrite mode select bit is ?? 3: effective only when the cpu rewrite mode select bit = ?? fix this bit to ??when the cpu rewrite mode select bit is ?? 4: write to this bit in program on ram [flash memory control registers (fmcr0 to fmcr2)] 0fe0 16 to 0fe2 16 figure 98 shows the flash memory control register 0. bit 0 of the flash memory control register 0 is the ry/by status flag used exclusively to read the operating status of the flash memory. during programming and erase operations, it is ? (busy). otherwise, it is ??(ready). bit 1 of the flash memory control register 0 is the cpu rewrite mode select bit. when this bit is set to ?? the mcu enters cpu rewrite mode. and then, software commands can be accepted. in cpu rewrite mode, the cpu becomes unable to access the inter- nal flash memory directly. therefore, use the control program in the internal ram for write to bit 1. to set this bit 1 to ?? it is nec- essary to write ??and then write ??in succession to bit 1. the bit can be set to ??by only writing ?? bit 2 of the flash memory control register 0 is the 8kb user block e/w mode enable bit. by setting this bit in combination with bit 4 (all user block e/w enable bit) of flash memory control register 2 (address 0fe0 16 ), erase/write to user block in cpu rewrite mode is disabled. bit 3 of the flash memory control register 0 is the flash memory re- set bit used to reset the control circuit of internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is ?? setting ??for this bit resets the control circuit. to release the reset, it is necessary to set this bit to ?? bit 5 of the flash memory control register 0 is the user rom area select bit and is valid only in the boot mode. setting this bit to ? in the boot mode switches an accessible area from the boot rom area to the user rom area. to use the cpu rewrite mode in the boot mode, set this bit to ?? note that when the microcomputer is booted up in the user rom area, only the user rom area is ac- cessible and bit 5 is invalid; on the other hand, when the microcomputer is in the boot mode, bit 5 is valid independent of the cpu rewrite mode. to rewrite bit 5, execute the user-original reprogramming control software transferred to the internal ram in advance. bit 6 of the flash memory control register 0 is the program status flag. this bit is set to ??when writing to flash memory is failed. when program error occurs, the block cannot be used. bit 7 of the flash memory control register 0 is the erase status flag. this bit is set to ??when erasing flash memory is failed. when erase error occurs, the block cannot be used.
7542 group rev.3.03 jul 11, 2008 page 76 of 117 rej03b0006-0303 notes 1: for this bit to be set to ?? the user needs to write a ??and then a ??to it in succession. for this bit to be set to ?? write ??only to this bit. 2: effective only when the suspend enable bit = ?? b7 b0 erase suspend enble bit (n otes 1) 0 : suspend invalid 1 : suspend valid erase suspend request bit (n otes 2) 0 : erase restart 1 : suspend request erase suspend flag 0 : erase active 1 : erase inactive (erase suspend mode) not used (do not write ??to this bit.) not used (do not write ??to this bit.) flash memory control register 1 (fmcr1: address : 0fe1 16 : initial value: 40 16 ) figure 99 shows the flash memory control register 1. bit 0 of the flash memory control register 1 is the erase suspend enable bit. by setting this bit to ?? the erase suspend mode to suspend erase processing temporarily when block erase com- mand is executed can be used. in order to set this bit to ?? writing ??and ??in succession to bit 0. in order to set this bit to ?? write ??only to bit 0. bit 1 of the flash memory control register 1 is the erase suspend request bit. by setting this bit to ??when erase suspend enable bit is ?? the erase processing is suspended. bit 6 of the flash memory control register 1 is the erase suspend flag. this bit is cleared to ??at the flash erasing. figure 100 shows the flash memory control register 2. bit 0 of the flash memory control register 1 is the all user block e/ w enable bit. by setting this bit to ?? erase/write to all user block (blocks 0, 1, 2) is disabled. as a result, error writing in program to write only to data block can be prevented. fig. 99 structure of flash memory control register 1 fig. 100 structure of flash memory control register 2 t able 10 erase/write disable setting cpu rewrite mode select bit 0 0 0 0 1 1 1 1 all user block e/w enable bit 0 0 1 1 0 0 1 1 8kb user block e/w enable bit 0 1 0 1 0 1 0 1 block 0: 8kb block 1: 8kb e/w disabled (reset) e/w disabled e/w disabled e/w disabled e/w disabled e/w disabled e/w disabled e/w enabled block 2: 16kb e/w disabled (reset) e/w disabled e/w disabled e/w disabled e/w disabled e/w disabled e/w enabled e/w enabled data block a: 2kb data block b: 2kb e/w disabled (reset) e/w disabled e/w disabled e/w disabled e/w enabled e/w enabled e/w enabled e/w enabled notes 1: for this bit to be set to ?? the user needs to write a ??and then a ??to it in succession. for this bit to be set to ?? write ??only to this bit. 2: effective only when the cpu rewrite mode select bit = ?? b7 b0 reserved bit (returns ??when read) reserved bits (do not write ??to this bit.) all user block e/w enable bit ( notes 1, 2) 0 : e/w disabled 1 : e/w enabled not used (do not write ??to this bit.) flash memory control register 2 (fmcr2: address : 0fe2 16 : initial value: 01 16 )
7542 group rev.3.03 jul 11, 2008 page 77 of 117 rej03b0006-0303 notes on cpu rewrite mode t ake the notes described below when rewriting the flash memory in cpu rewrite mode. operation speed during cpu rewrite mode, set the system clock to 4.0 mhz or less using the clock division ratio selection bits (bits 6 and 7 of ad- dress 003b 16 ). instructions inhibited against use the instructions which refer to the internal data of the flash memory cannot be used during cpu rewrite mode. interrupts inhibited against use the interrupts cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. w atchdog timer if the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely cleared during program or erase. reset reset is always valid. the mcu is activated using the boot mode at release of reset in the condition of cnvss = ?? so that the pro- gram will begin at the address which is stored in addresses fffc 16 and fffd 16 of the boot rom area. fig. 101 cpu rewrite mode set/release flowchart end start exec ute read array command or reset flash memory by setting flash memory reset bit (by wr it in g ? and then ??in succession) (note 3) si ngle-chip mode or boot mode set cpu mode register (note 1) us i ng software command executes erase, program, or other operation j u m p t o c o n t r o l p r o g r a m t r a n s f e r r e d t o i n t e r n a l r a m ( s u b s e q u e n t o p e r a t i o n s a r e e x e c u t e d b y c o n t r o l p r o g r a m i n t h i s r a m ) t r a n s f e r c p u r e w r i t e m o d e c o n t r o l p r o g r a m t o i n t e r n a l r a m n o t e s1 : s e t t h e m a i n c l o c k a s f o l l o w s d e p e n d i n g o n t h e c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s o f write 0 to cpu rewrite mode select bit s e t c p u r e w r i t e m o d e s e l e c t b i t t o 1 ( b y w r i t i n g 0 a n d t h e n 1 i n s u c c e s s i o n ) cp u mode register (bits 6, 7 of address 003b 16 ). 2 : as for setting of thes e bits, refer to table 10. 3 : before exiting the cpu rewrite mode after completing erase or program operation, s e t a l l u s e r b l o c k e / w e n a b l e b i t s e t 8 k b u s e r b l o c k e / w m o d e e n a b l e b i t (f o r s e t t i n g t o 1 ? b y w r i t i n g 0 a n d t h e n 1 i n s u c c e s s i o n ) ( note 2 ) s e t a l l u s e r b l o c k e / w e n a b l e b i t t o 0 s e t 8 k b u s e r b l o c k e / w m o d e e n a b l e b i t t o 0 a l w a y s b e s u r e t o e x e c u t e t h e r e a d a r r a y c o m m a n d o r r e s e t t h e f l a s h m e m o r y . figure 101 shows a flowchart for setting/releasing cpu rewrite mode.
7542 group rev.3.03 jul 11, 2008 page 78 of 117 rej03b0006-0303 software commands t able 11 lists the software commands. after setting the cpu rewrite mode select bit to ?? execute a soft- ware command to specify an erase or program operation. each software command is explained below. ?read array command (ff 16 ) the read array mode is entered by writing the command code ?f 16 ?in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the contents of the specified address are read out at the data bus (d 0 to d 7 ). the read array mode is retained until another command is written. ?read status register command (70 16 ) when the command code ?0 16 ?is written in the first bus cycle, the contents of the status register are read out at the data bus (d 0 to d 7 ) by a read in the second bus cycle. the status register is explained in the next section. ?clear status register command (50 16 ) this command is used to clear the bits sr4 and sr5 of the status register after they have been set. these bits indicate that opera- tion has ended in an error. to use this command, write the command code ?0 16 ?in the first bus cycle. ?program command (40 16 ) program operation starts when the command code ?0 16 ?is writ- ten in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming and verification) will start. whether the write operation is completed can be confirmed by _____ read status register or the ry/by status flag. when the program starts, the read status register mode is entered automatically and the contents of the status register is read at the data bus (d 0 to d 7 ). the status register bit 7 (sr7) is set to ??at the same time the write operation starts and is returned to ??upon completion of the write operation. in this case, the read status register mode re- mains active until the read array command (ff 16 ) is written. t able 11 list of software commands (cpu rewrite mode) the ry/by status flag of the flash memory control register is ? during write operation and ??when the write operation is com- pleted as is the status register bit 7. at program end, program results can be checked by reading the status register. fig. 102 program flowchart s t a r t w r i t e 4 0 1 6 r e a d s t a t u s r e g i s t e r p r o g r a m c o m p l e t e d n o y e s w r i t e a d d r e s s w r i t e d a t a sr4 = ?? p r o g r a m e r r o r n o y e s s r 7 = 1 ? o r r y / b y = 1 ? w r i t e command read array read status register clear status register program block erase mode first bus cycle second bus cycle address data (d 0 to d 7 ) mode address data (d 0 to d 7 ) write write write write write ? (note 4) ? ? ? ? ff 16 70 16 50 16 40 16 20 16 read write write ? wa (note 2) ba (note 3) srd (note 1) wd (note 2) d0 16 srd = status register data wa = write address, wd = write data ba = block address to be erased (input the maximum address of each block.) ? = ? denotes a given address in the user rom area.
7542 group rev.3.03 jul 11, 2008 page 79 of 117 rej03b0006-0303 ?block erase command (20 16 /d0 16 ) by writing the command code ?0 16 ?in the first bus cycle and the confirmation command code ?0 16 ?and the block address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. whether the block erase operation is completed can be confirmed by read status register or the ry/by status flag of flash memory control register. at the same time the block erase operation starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. the status register bit 7 (sr7) is set to ??at the same time the block erase operation starts and is returned to ??upon completion of the block erase operation. in this case, the read status register mode remains ac- tive until the read array command (ff 16 ) is written. the ry/by status flag is ??during block erase operation and ? when the block erase operation is completed as is the status reg- ister bit 7. after the block erase ends, erase results can be checked by read- ing the status register. for details, refer to the section where the status register is detailed. fig. 103 erase flowchart write ?0 16 ?0 16 block address erase completed (write read command ff 16 ) no yes start write sr5 = ??? erase error yes no sr7 = ?? or ry/by = ?? read status register
7542 group rev.3.03 jul 11, 2008 page 80 of 117 rej03b0006-0303 t able 12 definition of each bit in status register status register the status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. it can be read in the following ways: (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input. also, the status register can be cleared by writing the clear status register command (50 16 ). after reset, the status register is set to ?0 16 ? t able 12 shows the status register. each bit in this register is ex- plained below. sequencer status (sr7) the sequencer status indicates the operating status of the flash memory. this bit is set to ??(busy) during write or erase operation and is set to ??when these operations ends. after power-on, the sequencer status is set to ??(ready). erase status (sr5) the erase status indicates the operating status of erase operation. if an erase error occurs, it is set to ?? when the erase status is cleared, it is reset to ?? program status (sr4) the program status indicates the operating status of write opera- tion. when a write error occurs, it is set to ?? the program status is reset to ??when it is cleared. if ??is written for any of the sr5 and sr4 bits, the read array, program, and block erase commands are not accepted. before ex- ecuting these commands, execute the clear status register command (50 16 ) and clear the status register. also, if any commands are not correct, both sr5 and sr4 are set to ?? each bit of srd bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) sequencer status reserved erase status program status reserved reserved reserved reserved status name ? ready - terminated in error terminated in error - - - - ? busy - terminated normally terminated normally - - - - definition
7542 group rev.3.03 jul 11, 2008 page 81 of 117 rej03b0006-0303 full status check by performing full status check, it is possible to know the execu- tion results of erase and program operations. figure 104 shows a full status check flowchart and the action to be taken when each error occurs. fig. 104 full status check flowchart and remedial procedure for errors read status register s r 4 = 1 a n d s r5 = 1 ? no y e s sr5 = ??? y e s er a s e e r r o r no sr4 = ??? y e s n o command sequence error program error end (block erase, program) e x e c u t e t h e c l e a r s t a t u s r e g i s t e r c o m m a n d ( 5 0 1 6 ) t o c l e a r t h e s t a t u s r e g i s t e r . t r y p e r f o r m i n g t h e o p e r a t i o n o n e m o r e t i m e a f t e r c o n f i r m i n g t h a t t h e c o m m a n d i s e n t e r e d c o r r e c t l y . s h o u l d a n e r a s e e r r o r o c c u r , t h e b l o c k i n e r r o r c a n n o t b e u s e d . note : when one of sr5 and sr4 is set to ?, none of the read array, program, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. s h o u l d a p r o g r a m e r r o r o c c u r , t h e b l o c k i n e r r o r c a n n o t b e u s e d .
7542 group rev.3.03 jul 11, 2008 page 82 of 117 rej03b0006-0303 functions to inhibit rewriting flash memory version to prevent the contents of internal flash memory from being read out or rewritten easily, this mcu incorporates a rom code protect function for use in parallel i/o mode and an id code check func- tion for use in standard serial i/o mode. (1) rom code protect function the rom code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the rom code protect control address (address ffdb 16 ) in paral- lel i/o mode. figure 105 shows the rom code protect control address (address ffdb 16 ). (this address exists in the user rom area.) if one or both of the pair of rom code protect bits is set to ?? the rom code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. the rom code protect is implemented in two levels. if level 2 is se- lected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to ?0? the rom code protect is turned off, so that the contents of internal flash memory can be readout or modified. once the rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/o or cpu rewrite mode to rewrite the contents of the rom code protect reset bits. rewriting of only the rom code protect control address (address ffdb 16 ) cannot be performed. when rewriting the rom code pro- tect reset bit, rewrite the whole user rom area (block 0) containing the rom code protect control address. fig. 105 structure of rom code protect control address r o m c o d e p r o t e c t c o n t r o l a d d r e s s ( a d d r e s s f f d b 1 6 ) r o m c p ( f f 1 6 w h e n s h i p p e d ) reserved bits (??at read/write) rom code protect level 2 set bits (romcp2) ( notes 1, 2 ) b3b2 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled rom code protect reset bits ( note 3 ) b5b4 0 0: protect removed 0 1: protect set bits effective 1 0: protect set bits effective 1 1: protect set bits effective rom code protect level 1 set bits (romcp1) ( note 1 ) b7b6 0 0: protect enabled 0 1: protect enabled 1 0: protect enabled 1 1: protect disabled b 0 b 7 n o t e s1 : w h e n r o m c o d e p r o t e c t i s t u r n e d o n , t h e i n t e r n a l f l a s h m e m o r y i s p r o t e c t e d a g a i n s t r e a d o u t o r m o d i f i c a t i o n i n p a r a l l e l i / o m o d e . 2 : w h e n r o m c o d e p r o t e c t l e v e l 2 i s t u r n e d o n , r o m c o d e r e a d o u t b y a s h i p m e n t i n s p e c t i o n l s i t e s t e r , e t c . a l s o i s i n h i b i t e d . 3 : t h e r o m c o d e p r o t e c t r e s e t b i t s c a n b e u s e d t o t u r n o f f r o m c o d e p r o t e c t l e v e l 1 a n d r o m c o d e p r o t e c t l e v e l 2 . h o w e v e r , s i n c e t h e s e b i t s c a n n o t b e m o d i f i e d i n p a r a l l e l i / o m o d e , t h e y n e e d t o b e r e w r i t t e n i n s e r i a l i / o m o d e o r c p u r e w r i t e m o d e . 11
7542 group rev.3.03 jul 11, 2008 page 83 of 117 rej03b0006-0303 (2) id code check function use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the pro- grammer is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, and its areas are ffd4 16 to ffda 16 . write a pro- gram which has had the id code preset at these addresses to the flash memory. fig. 106 id code store addresses rom code protect control id7 id6 id5 id4 id3 id2 id1 ffdb 16 ffda 16 ffd9 16 ffd8 16 ffd7 16 ffd6 16 ffd5 16 ffd4 16 address interrupt vector area
7542 group rev.3.03 jul 11, 2008 page 84 of 117 rej03b0006-0303 parallel i/o mode the parallel i/o mode is used to input/output software commands, address and data in parallel for operation (read, program and erase) to internal flash memory. use the external device (writer) only for 7542 group (flash memory version). for details, refer to the users manual of each writer manufacturer. ?user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 97 can be rewritten. both areas of flash memory can be operated on in the same way. the boot rom area is 4 kbytes in size and located at addresses f000 16 through ffff 16 . make sure program and block erase op- erations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 4 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the fac- tory. therefore, using the mcu in standard serial i/o mode, do not rewrite to the boot rom area.
7542 group rev.3.03 jul 11, 2008 page 85 of 117 rej03b0006-0303 standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. this i/o is clock synchronized serial. this mode requires a purpose-specific pe- ripheral unit. the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory rewrite (uses the cpu rewrite mode), rewrite data input and so forth. the standard serial i/o mode is started when the microcomputer is reset and the cnv ss pin high after pulling the p3 7 (rp) pin low, p3 2 (ce) pin high, p0 6 /s clk2 pin low and p0 5 /txd 2 pin high. (in the ordinary microcomputer mode, set cnvss pin to ??level.) this control program is written in the boot rom area when the product is shipped from renesas. accordingly, make note of the fact that the standard serial i/o mode cannot be used if the boot rom area is rewritten in parallel i/o mode. the standard serial i/o mode has standard serial i/o mode 1 of the clock synchronous serial and the standard serial i/o mode 2 of the clock asynchronous serial. t able 13 lists the description of pin function (standard serial i/o mode 1). figures 107 to 109 show the pin connections for the standard serial i/o mode 1. t able 14 lists the description of pin function (standard serial i/o mode 2). figures 112 to 114 show the pin connections for the standard serial i/o mode 2. in standard serial i/o mode, only the user rom area shown in figure 97 can be rewritten. the boot rom area cannot be written. in standard serial i/o mode, a 7-byte id code is used. when there is data in the flash memory, this function determines whether the id code sent from the peripheral unit (programmer) and those writ- ten in the flash memory match.the commands sent from the peripheral unit (programmer) are not accepted unless the id code matches.
7542 group rev.3.03 jul 11, 2008 page 86 of 117 rej03b0006-0303 pin name signal name i/o v cc ,v ss power supply i cnv ss cnv ss i reset reset input i x in clock input i x out clock output o v ref reference voltage input i p0 0 ?0 3 i/o port p0 i/o p0 4 rxd input i p0 5 txd output o p0 6 s clk input i p0 7 busy output o p1 0 ?1 4 i/o port p1 i/o p2 0 ?2 7 i/o port p2 i/o p3 0 , p3 1 , p3 3 ?3 6 i/o port p3 i/o p3 2 ce input i p3 7 rp input i (1) standard serial i/o mode 1 t able 13 description of pin function (standard serial i/o mode 1) function apply 2.7 to 5.5 v to the vcc pin and 0 v to the vss pin. after input of port is set, input ??level. reset input pin. system operates when reset pin is set to ??level after cnvss pin is set to ??level. connect an oscillation circuit between the x in and x out pins. as for the connection method, refer to the ?lock generating circuit? (when system operates only by the on-chip oscillator, an external circuit is not required.) apply reference voltage of a/d to this pin. input ??or ??level, or keep open. serial data input pin. serial data output pin. serial clock input pin. busy signal output pin. input ??or ??level, or keep open. input ??or ??level, or keep open. input ??or ??level, or keep open. input ??level. input ??level.
7542 group rev.3.03 jul 11, 2008 page 87 of 117 rej03b0006-0303 fig. 107 pin connection diagram in standard serial i/o mode 1 (plqp0032gb-a package) p0 7 (led 07 )/s rdy2 p1 0 /r x d 1 /cap 0 p1 1 /t x d 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 / an 0 p2 1 / an 1 32 31 30 29 28 27 26 25 p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 p3 0 (led 10 )/cap 1 v ss x out x in 9 10 11 12 13 14 15 16 8 7 6 5 3 14 v cc cnv ss reset p2 2 /an 2 p0 5 (led 05 )/txd 2 20 17 18 19 21 24 p0 2 (led 02 )/cmp 1 p0 4 (led 04 )/rxd 2 p0 3 (led 03 )/tx out p0 6 (led 06 )/s clk2 23 22 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 m37542fxgp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref 2 vss busy "h" input vcc cnv ss reset rxd txd s clk "l" input note note. connect the oscillation circuit to x in and x out . (package type: plqp0032gb-a)
7542 group rev.3.03 jul 11, 2008 page 88 of 117 rej03b0006-0303 fig. 108 pin connection diagram in standard serial i/o mode 1 (prsp0036ga-a package) fig. 109 pin connection diagram in standard serial i/o mode 1 (prdp0032ba-a package) 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 cnv ss x out x in v ss p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 vcc v ref p0 5 (led 05 )/txd 2 p1 0 /r x d 1 /cap 0 p2 6 /an 6 p2 7 /an 7 p1 1 /t x d 1 p1 2 /s clk1 p1 3 /s rdy1 p2 3 /an 3 p2 2 /an 2 p2 1 /an 1 p2 0 /an 0 p3 1 (led 11 )/cmp 2 p3 6 (led 16 )/int 1 p2 4 /an 4 p2 5 /an 5 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 reset m37542fxfp p1 4 /cntr 0 p3 5 (led 15 ) p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 7 (led 17 )/int 0 p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out busy s clk t x d r x d l input h input reset vcc vss cnv ss note note. connect the oscillation circuit to x in and x out . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnv ss p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 v cc x in x out v ss p1 1 /t x d 1 p1 0 /r x d 1 /cap 0 p0 7 (led 07 )/s rdy2 p0 6 (led 06 )/s clk2 p0 5 (led 05 )/txd 2 p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 p2 5 /an 5 v ref reset p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 m37542fxsp 32 14 15 16 p3 4 (led 14 ) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 p0 3 (led 03 )/tx out p0 2 (led 02 )/cmp 1 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 busy s clk t x d r x d l input h input reset vcc vss cnv ss note note. connect the oscillation circuit to x in and x out . (package type: prsp0036ga-a) (package type: prdp0032ba-a)
7542 group rev.3.03 jul 11, 2008 page 89 of 117 rej03b0006-0303 fig. 110 handling example of control pins in standard serial i/o mode 1 m37542 flash memory version target board reset x in x out user reset circuit to user system circuit t x d(p0 5 ) s clk (p0 6 ) r x d(p0 4 ) busy(p0 7 ) v ss (p3 2 ) v cc note 1 (p3 7 ) cnv ss note 2 connect the user reset circuit to the reset pin with the shortest possible wiring. in the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memory version, from the mcu by a jumper switch. connect the cnvss pin to the vss pin with the shortest possible wiring. in the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memor y version , from the mcu b y a j um p er switch. notes 1: 2: ?standard serial i/o mode 1 figure 110 shows the handling example of control pins on the user system board when the standard serial i/o mode 1 is used. refer to the serial programmer manual of your programmer to handle pins controlled by the programmer.
7542 group rev.3.03 jul 11, 2008 page 90 of 117 rej03b0006-0303 fig. 111 timing diagram in standard serial i/o mode 1 power source reset cnv ss p3 7 (rp) p3 2 (ceb) p0 7 (busy) p0 6 (s clk2 ) p0 5 (txd 2 ) p0 4 (rxd 2 ) td(port-cnv ss ) th(cnv ss -reset) th(cnv ss -port) td(cnv ss -reset) td(reset-sclk) symbol td(port-cnvss) td(cnvss-reset) td(reset-sclk) th(reset-cnvss) th(cnvss-port) ratings unit ms ms ms ms ms min. 1 1 0.05 1 1 t yp. - - - - - max. - - 0.5 - - note: keep input of p0 6 ??until p0 7 turns ?? (note)
7542 group rev.3.03 jul 11, 2008 page 91 of 117 rej03b0006-0303 pin name signal name i/o v cc ,v ss power supply i cnv ss cnv ss i reset reset input i x in clock input i x out clock output o v ref reference voltage input i p0 0 ?0 3 i/o port p0 i/o p0 4 rxd input i p0 5 txd output o p0 6 s clk input i p0 7 busy output o p1 0 ?1 4 i/o port p1 i/o p2 0 ?2 7 i/o port p2 i/o p3 0 , p3 1 , p3 3 ?3 6 i/o port p3 i/o p3 2 ce input i p3 7 rp input i i (2) standard serial i/o mode 2 t able 14 description of pin function (standard serial i/o mode 2) function apply 2.7 to 5.5 v to the vcc pin and 0 v to the vss pin. after input of port is set, input ??level. reset input pin. system operates when reset pin is set to ??level after cnvss pin is set to ??level. connect an oscillation circuit between the x in and x out pins. as for the connection method, refer to the ?lock generating circuit? (when system operates only by the on-chip oscillator, an external circuit is not required.) apply reference voltage of a/d to this pin. input ??or ??level, or keep open. serial data input pin. serial data output pin. input ??level. busy signal output pin. input ??or ??level, or keep open. input ??or ??level, or keep open. input ??or ??level, or keep open. input ??level. input ??level.
7542 group rev.3.03 jul 11, 2008 page 92 of 117 rej03b0006-0303 p0 7 (led 07 )/s rdy2 p1 0 /r x d 1 /cap 0 p1 1 /t x d 1 p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 / an 0 p2 1 / an 1 32 31 30 29 28 27 26 25 p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 p3 0 (led 10 )/cap 1 v ss x out x in 9 10 11 12 13 14 15 16 8 7 6 5 3 14 v cc cnv ss rese t p2 2 /an 2 p0 5 (led 05 )/txd 2 20 17 18 19 21 24 p0 2 (led 02 )/cmp 1 p0 4 (led 04 )/rxd 2 p0 3 (led 03 )/tx out p0 6 (led 0 6 )/s clk2 23 22 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 m37542fxgp p2 3 /an 3 p2 4 /an 4 p2 5 /an 5 v ref 2 vss ??input vcc cnv ss reset rxd txd busy "l" input ??input note. connect the oscillation circuit to x in and x out . note fig. 112 pin connection diagram in standard serial i/o mode 2 (plqp0032gb-a package) (package type: plqp0032gb-a)
7542 group rev.3.03 jul 11, 2008 page 93 of 117 rej03b0006-0303 fig. 113 pin connection diagram in standard serial i/o mode 2 (prsp0036ga-a package) fig. 114 pin connection diagram in standard serial i/o mode 2 (prdp0032ba-a package) 10 1 2 3 4 6 7 8 9 11 12 14 15 16 5 13 17 18 36 35 34 33 31 30 26 25 24 23 22 21 20 19 32 27 29 28 cnv ss x out x in v ss p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 vcc v ref p0 5 (led 05 )/txd 2 p1 0 /r x d 1 /cap 0 p2 6 /an 6 p2 7 /an 7 p1 1 /t x d 1 p1 2 /s clk1 p1 3 /s rdy1 p2 3 /an 3 p2 2 /an 2 p2 1 /an 1 p2 0 /an 0 p3 1 (led 11 )/cmp 2 p3 6 (led 16 )/int 1 p2 4 /an 4 p2 5 /an 5 p0 6 (led 06 )/s clk2 p0 7 (led 07 )/s rdy2 reset m37542fxfp p1 4 /cntr 0 p3 5 (led 15 ) p3 4 (led 14 ) p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 7 (led 17 )/int 0 p0 0 (led 00 )/cap 0 p0 1 (led 01 )/cmp 0 p0 2 (led 02 )/cmp 1 p0 3 (led 03 )/tx out ??input busy t x d r x d ??input ??input reset vcc vss cnv ss note. connect the oscillation circuit to x in and x out . note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 cnv ss p1 2 /s clk1 p1 3 /s rdy1 p1 4 /cntr 0 p2 0 /an 0 p2 1 /an 1 p2 2 /an 2 p2 3 /an 3 p2 4 /an 4 v cc x in x out v ss p1 1 /t x d 1 p1 0 /r x d 1 /cap 0 p0 7 (led 07 )/s rdy2 p0 6 (led 06 )/s clk 2 p0 5 (led 05 )/txd 2 p0 4 (led 04 )/rxd 2 p3 0 (led 10 )/cap 1 p2 5 /an 5 v ref reset p3 3 (led 13 )/int 1 p3 2 (led 12 )/cmp 3 p3 1 (led 11 )/cmp 2 m37542fxsp 32 14 15 16 p3 4 (led 14 ) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 p0 3 (led 03 )/tx out p0 2 (led 02 )/cmp 1 p0 1 (led 01 )/cmp 0 p0 0 (led 00 )/cap 0 p3 7 (led 17 )/int 0 ??input busy t x d r x d ??input ??input reset vcc vss cnv ss note. connect the oscillation circuit to x in and x out . note (package type: prsp0036ga-a) (package type: prdp0032ba-a)
7542 group rev.3.03 jul 11, 2008 page 94 of 117 rej03b0006-0303 m37542 flash memory version target board reset x in x out user reset circuit to user system circuit t x d(p0 5 ) s clk (p0 6 ) r x d(p0 4 ) busy(p0 7 ) v ss (p3 2 ) v cc note 1 note 2 (p3 7 ) cnv ss connect the user reset circuit to the reset pin with the shortest possible wiring. in the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memory version, from the mcu by a jumper switch. connect the cnvss pin to the vss pin with the shortest possible wiring. in the normal microcomputer mode, disconnect a wiring of a serial rewrite circuit, which is for the flash memor y version , from the mcu b y a j um p er switch. notes 1: 2: fig. 115 handling example of control pins in standard serial i/o mode 2 ?standard serial i/o mode 2 figure 115 shows the handling example of control pins on the user system board when the standard serial i/o mode 2 is used. refer to the serial programmer manual of your programmer to handle pins controlled by the programmer.
7542 group rev.3.03 jul 11, 2008 page 95 of 117 rej03b0006-0303 fig. 116 timing diagram in standard serial i/o mode 2 power source reset cnv ss p3 7 (rp) p3 2 (ceb) p0 6 (s clk2 ) p0 5 (txd 2 ) p0 4 (rxd 2 ) td(port-cnv ss ) th(cnv ss -reset) th(cnv ss -port) td(cnv ss -reset) symbol td(port-cnvss) td(cnvss-reset) th(reset-cnvss) th(cnvss-port) ratings unit ms ms ms ms min. 1 1 1 1 t yp. - - - - max. - - - - note: in the standard serial i/o2, set p0 6 and p0 7 as follows; p0 6 : input ??level. p0 7 : busy signal output pin. keep open.
7542 group rev.3.03 jul 11, 2008 page 96 of 117 rej03b0006-0303 electrical characteristics 1.absolute maximum ratings t able 15 absolute maximum ratings ?.3 to 6.5 ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 ?.3 to v cc + 0.3 300 ( note ) ?0 to 85 ?0 to 125 power source voltage input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 , v ref input voltage reset, x in input voltage cnv ss output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 , x out power dissipation operating temperature storage temperature v v v v v mw ? ? v cc v i v i v i v o p d t opr t stg conditions symbol ratings unit parameter all voltages are based on v ss . when an input voltage is measured, output transistors are cut off. ta = 25? note: 200 mw for the plqp0032gb-a package product.
7542 group rev.3.03 jul 11, 2008 page 97 of 117 rej03b0006-0303 recommended operating conditions t able 16 recommended operating conditions (1) (flash rom version: v cc = 2.7 to 5.5v, mask rom version: v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 v cc v cc v cc v cc 0.2v cc 0.8 0.2v cc 0.16v cc ?0 80 80 ?0 40 40 4.0 2.4 2.7 2.2 2.7 4.5 4.0 2.4 2.7 2.2 2.7 4.0 2.4 2.7 2.2 2.7 2.0 0.8v cc 2.0 0.8v cc 0 0 0 0 min. t yp. max. symbol parameter unit power source voltage (high-, middle-speed mode) (ceramic) (double-speed mode) power source voltage (high-, middle-speed mode) (rc) power source voltage analog reference voltage ??input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) ??input voltage reset, x in ??input voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input voltage (ttl input level selected) p1 0 , p1 2 , p1 3 , p3 6 , p3 7 (note 1) ??input voltage reset, cnv ss ??input voltage x in ??total peak output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??total peak output current (note 2) p1 0 ?1 4 , p2 0 ?2 7 ??total peak output current (note 2) p0 0 ?0 7 , p3 0 ?3 7 ??total average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??total average output current (note 2) p1 0 ?1 4 , p2 0 ?2 7 ??total average output current (note 2) p0 0 ?0 7 , p3 0 ?3 7 f(x in ) = 8 mhz mask rom flash rom f(x in ) = 4 mhz mask rom flash rom f(x in ) = 2 mhz mask rom flash rom f(x in ) = 8 mhz mask rom flash rom f(x in ) = 6.5 mhz mask rom flash rom f(x in ) = 2 mhz mask rom flash rom f(x in ) = 1 mhz mask rom flash rom f(x in ) = 4 mhz mask rom flash rom f(x in ) = 2 mhz mask rom flash rom f(x in ) = 1 mhz mask rom flash rom 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 limits v cc v ss v ref v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) v v v v v v v v v v v v v v v v v v v v v v v v v ma ma ma ma ma ma note 1: vcc = 4.0 to 5.5v 2: the total output current is the sum of all the currents flowing through all the applicable ports. the total average current is an average value measured over 100 ms. the total peak current is the peak value of all the currents.
7542 group rev.3.03 jul 11, 2008 page 98 of 117 rej03b0006-0303 recommended operating conditions (continued) t able 17 recommended operating conditions (2) (flash rom version: v cc = 2.7 to 5.5v, mask rom version: v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) ??peak output current (note 1) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??peak output current (note 1) p0 0 ?0 7 , p3 0 ?3 7 (drive capacity = ?? p1 0 ?1 4 , p2 0 ?2 7 ??peak output current (note 1) p0 0 ?0 7 , p3 0 ?3 7 (drive capacity = ?? ??average output current (note 2) p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??average output current (note 2) p0 0 ?0 7 , p3 0 ?3 7 (drive capacity = ?? p1 0 ?1 4 , p2 0 ?2 7 ??average output current (note 2) p0 0 ?0 7 , p3 0 ?3 7 (drive capacity = ?? oscillation frequency (note 3) mask rom: v cc = 4.5 to 5.5 v at ceramic oscillation or external clock input flash rom: v cc = 4.5 to 5.5 v double-speed mode oscillation frequency (note 3) mask rom: v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input flash rom: v cc = 4.0 to 5.5 v double-speed mode oscillation frequency (note 3) mask rom: v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input flash rom: v cc = 2.7 to 5.5 v double-speed mode oscillation frequency (note 3) mask rom: v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input double-speed mode oscillation frequency (note 3) mask rom: v cc = 4.0 to 5.5 v at ceramic oscillation or external clock input flash rom: v cc = 4.0 to 5.5 v high-, middle-speed mode oscillation frequency (note 3) mask rom: v cc = 2.4 to 5.5 v at ceramic oscillation or external clock input flash rom: v cc = 2.7 to 5.5 v high-, middle-speed mode oscillation frequency (note 3) mask rom: v cc = 2.2 to 5.5 v at ceramic oscillation or external clock input high-, middle-speed mode oscillation frequency (note 3) mask rom: v cc = 4.0 to 5.5 v at rc oscillation flash rom: v cc = 4.0 to 5.5 v high-, middle-speed mode oscillation frequency (note 3) mask rom: v cc = 2.4 to 5.5 v at rc oscillation flash rom: v cc = 2.7 to 5.5 v high-, middle-speed mode oscillation frequency (note 3) mask rom: v cc = 2.2 to 5.5 v at rc oscillation high-, middle-speed mode symbol parameter limits max. t yp. min. ?0 10 30 ? 5 15 8 6.5 2 1 8 4 2 4 2 1 notes 1: the peak output current is the peak current flowing in each port. 2: the average output current i ol (avg), i oh (avg) in an average value measured over 100 ms. 3: when the oscillation frequency has a duty cycle of 50 %. i oh(peak) i ol(peak) i ol(peak) i oh(avg) i ol(avg) i ol(avg) f(x in ) ma ma ma ma ma ma mhz mhz mhz mhz mhz mhz mhz mhz mhz mhz unit
7542 group rev.3.03 jul 11, 2008 page 99 of 117 rej03b0006-0303 electrical characteristics t able 18 electrical characteristics (1) (flash rom version: v cc = 2.7 to 5.5v, mask rom version: v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. t yp. max. symbol parameter limits unit i oh = ? ma v cc = 4.0 to 5.5 v i oh = ?.0 ma mask rom: v cc = 2.2 to 5.5 v flash rom: v cc = 2.7 to 5.5 v i ol = 5 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma mask rom: v cc = 2.2 to 5.5 v flash rom: v cc = 2.7 to 5.5 v i ol = 15 ma v cc = 4.0 to 5.5 v i ol = 1.5 ma v cc = 4.0 to 5.5 v i ol = 1.0 ma mask rom: v cc = 2.2 to 5.5 v flash rom: v cc = 2.7 to 5.5 v v i = v cc (pin floating. pull up transistors ?ff? v i = v cc v i = v cc v i = v ss (pin floating. pull up transistors ?ff? v i = v ss v i = v ss v i = v ss (pull up transistors ?n? when clock stopped v cc = 5.0 v, ta = 25 ? v cc = 5.0 v, ta = 25 ? t est conditions v cc ?.5 v cc ?.0 2.0 1000 62.5 ??output voltage p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 (note 1) ??output voltage p0 0 ?0 7 , p3 0 ?3 7 (drive capacity = ?? p1 0 ?1 4 , p2 0 ?2 7 ??output voltage p0 0 ?0 7 , p3 0 ?3 7 (drive capacity = ?? hysteresis cntr 0 , int 0 , int 1 , cap 0 , cap 1 (note 2) p0 0 ?0 7 (note 3) hysteresis r x d 0 , s clk0 , r x d 1 , s clk1 hysteresis reset ??input current p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input current reset ??input current x in ??input current p0 0 ?0 7 , p1 0 ?1 4 , p2 0 ?2 7 , p3 0 ?3 7 ??input current reset ??input current x in ??input current p0 0 ?0 7 , p3 0 ?3 7 ram hold voltage on-chip oscillator oscillation frequency oscillation stop detection circuit detection frequency 1.5 0.3 1.0 2.0 0.3 1.0 5.0 5.0 ?.0 ?.0 ?.5 5.5 3000 187.5 v v v v v v v v v v v a a a a a a ma v khz khz v oh v ol v ol v t+ ? t v t+ ? t v t+ ? t i ih i ih i ih i il i il i il i il v ram r osc d osc 0.4 0.5 0.5 4.0 ?.0 ?.2 2000 125 notes 1: p1 1 is measured when the p1 1 /t x d 1 p-channel output disable bit of the uart1 control register (bit 4 of address 001b 16 ) is ?? 2: r x d 1 , s clk1 , int 0 , and int 1 (p3 6 selected) have hysteresises only when bits 0 to 2 of the port p1p3 control register are set to ??(cmos level). 3: it is available only when operating key-on wake up.
7542 group rev.3.03 jul 11, 2008 page 100 of 117 rej03b0006-0303 electrical characteristics (continued) t able 19 electrical characteristics (2) (flash rom version: v cc = 2.7 to 5.5v, mask rom version: v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. t yp. max. symbol parameter limits unit t est conditions power source current 9.0 7.5 6.5 5.5 5.0 4.2 1.2 2.8 3.2 2.4 2.2 1.9 1.0 1.3 0.6 1.0 3.2 2.6 0.6 0.4 1.0 3.0 10 10 ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma ma a a a a i cc 5.5 4.8 3.5 3.0 2.0 1.7 0.4 1.0 1.5 1.4 0.9 1.0 0.35 0.65 0.2 0.55 1.6 1.2 0.2 0.6 0.2 0.12 0.5 0.5 0.1 0.55 f(x in ) = 8 mhz output transistors ?ff f(x in ) = 2 mhz, mask rom: v cc = 2.2 v flash rom: v cc = 2.7 v output transistors ?ff on-chip oscillator operation mode, output transistors ?ff f(x in ) = 8 mhz (in wit state), functions except timer 1 disabled, output transistors ?ff f(x in ) = 2 mhz, mask rom: v cc = 2.2 v flash rom: v cc = 2.7 v (in wit state), functions except timer 1 disabled, output transistors ?ff on-chip oscillator operation mode, (in wit state), functions except timer 1 disabled, output transistors ?ff increment when a/d conversion is executed f(x in ) = 8 mhz, v cc = 5 v all oscillation stopped (in stp state) output transistors ?ff double-speed mode mask rom flash rom high-speed mode mask rom flash rom middle-speed mode mask rom flash rom high-speed mode mask rom flash rom frequency/1 mask rom flash rom frequency/2 mask rom flash rom frequency/8 mask rom flash rom frequency/128 mask rom flash rom mask rom flash rom mask rom flash rom mask rom flash rom mask rom flash rom ta = 25 ? mask rom flash rom ta = 85 ? mask rom flash rom note: increment when a/d conversion is executed includes the reference power source input current (iv ref ).
7542 group rev.3.03 jul 11, 2008 page 101 of 117 rej03b0006-0303 a/d converter characteristics t able 20 a/d converter characteristics (v cc = 2.7 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) resolution absolute accuracy conversion time ladder resistor reference power source input current a/d port input current min. t yp. max. symbol parameter limits unit t est conditions ta = 25 ? mask rom v cc = v ref = 2.7 to 5.5 v flash rom ad conversion clock = f(x in )/2 ad conversion clock = f(x in ) v ref = 5.0 v v ref = 3.0 v bits lsb tc(x in ) k ? a a 10 ?3 ?4 122 61 200 120 5.0 t conv r ladder i vref i i(ad) 55 150 90 50 30 note: ad conversion accuracy may be low under the following conditions; (1) when the v ref voltage is set to be lower than the v cc voltage, an analog circuit in this microcomputer is affected by noise. the accuracy is lower than the case the v ref voltage is the same as v cc voltage. (2) when the v ref voltage is 3.0 v or less at the low temperature, the ad conversion accuracy may be very lower than at room temperature. when system is used at low temperature, that v ref is 3.0 v or more is recommended. electrical characteristics of 7542 group flash memory t able 21 electrical characteristics of 7542 group flash memory symbol parameter program/erase endurance (note 1) byte program time 2kbyte-block block erase time 8kbyte-block 16kbyte-block t ime delay from suspend request until erase suspend erase suspend request interval program, erase voltage read voltage program, erase temperature data hold time t d(sr-es) note 1. definition of program and erase the program and erase endurance shows an erase endurance for every block. if the program and erase endurance is ??times (n = 100), ??times erase can be performed for every block. for example, if performing 1-byte write to the distinct addresses on block a of 2kbyte block 2048 times and then erasing that b lock, program and erase endurance is counted as one time. however, do not perform multiple programs to the same address for one time erase. (disable overwriting). limits unit min. 100 10 2.7 2.7 0 20 t yp. 50 0.2 0.4 0.7 max. 400 9 9 9 8 5.5 5.5 60 times s s s s ms ms v v ? year t est conditions ta = 55 ? fig. 117 time delay from suspend request until erase suspend t d(sr-es) erase-suspend request (interrupt request) erase suspend flag
7542 group rev.3.03 jul 11, 2008 page 102 of 117 rej03b0006-0303 t iming requirements t able 22 timing requirements (1) (flash rom version: v cc = 4.0 to 5.5v, mask rom version: v cc = 4.0 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. t yp. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , cap 0 , cap 1 input ??pulse width (note 1) cntr 0 , int 0 , int 1 , cap 0 , cap 1 input ??pulse width (note 1) serial i/o1, serial i/o2 clock input cycle time (note 2) serial i/o1, serial i/o2 clock input ??pulse width (note 2) serial i/o1, serial i/o2 clock input ??pulse width (note 2) serial i/o1, serial i/o2 input set up time serial i/o1, serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) 2 125 50 50 200 80 80 800 370 370 220 100 s ns ns ns ns ns ns ns ns ns ns ns t able 23 timing requirements (2) ( flash rom version: v cc = 2.7 to 5.5v, mask rom version: v cc = 2.4 to 5.5 v , v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. t yp. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , cap 0 , cap 1 input ??pulse width (note 1) cntr 0 , int 0 , int 1 , cap 0 , cap 1 input ??pulse width (note 1) serial i/o1, serial i/o2 clock input cycle time (note 2) serial i/o1, serial i/o2 clock input ??pulse width (note 2) serial i/o1, serial i/o2 clock input ??pulse width (note 2) serial i/o1, serial i/o2 input set up time serial i/o1, serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) 2 250 100 100 500 230 230 2000 950 950 400 200 s ns ns ns ns ns ns ns ns ns ns ns notes 1: as for cap 0 , cap 1 , it is the value when noise filter is not used. 2: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o is selected), the rating values are divide d by 4. in this time, bit 6 of the serial i/o2 control register (address 0030 16 ) is set to ??(clock synchronous serial i/o is selected). when bit 6 of the serial i/o2 control register is ??(clock asynchronous serial i/o is selected), the rating values are divide d by 4. notes 1: as for cap 0 , cap 1 , it is the value when noise filter is not used. 2: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4. in this time, bit 6 of the serial i/o2 control register (address 0030 16 ) is set to ??(clock synchronous serial i/o is selected). when bit 6 of the serial i/o2 control register is ??(clock asynchronous serial i/o is selected), the rating values are divide d by 4.
7542 group rev.3.03 jul 11, 2008 page 103 of 117 rej03b0006-0303 t able 24 timing requirements (3) (mask rom version: v cc = 2.2 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) (this is only for the mask rom version.) min. t yp. max. symbol parameter limits unit reset input ??pulse width external clock input cycle time external clock input ??pulse width external clock input ??pulse width cntr 0 input cycle time cntr 0 , int 0 , int 1 , cap 0 , cap 1 input ??pulse width (note 1) cntr 0 , int 0 , int 1 , cap 0 , cap 1 input ??pulse width (note 1) serial i/o1, serial i/o2 clock input cycle time (note 2) serial i/o1, serial i/o2 clock input ??pulse width (note 2) serial i/o1, serial i/o2 clock input ??pulse width (note 2) serial i/o1, serial i/o2 input set up time serial i/o1, serial i/o2 input hold time t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (cntr 0 ) t wh (cntr 0 ) t wl (cntr 0 ) t c (s clk1 ) t wh (s clk1 ) t wl (s clk1 ) t su (rxd 1 ? clk1 ) t h (s clk1 ?xd 1 ) 2 500 200 200 1000 460 460 4000 1900 1900 800 400 s ns ns ns ns ns ns ns ns ns ns ns notes 1: as for cap 0 , cap 1 , it is the value when noise filter is not used. 2: in this time, bit 6 of the serial i/o1 control register (address 001a 16 ) is set to ??(clock synchronous serial i/o is selected). when bit 6 of the serial i/o1 control register is ??(clock asynchronous serial i/o1 is selected), the rating values are divid ed by 4. in this time, bit 6 of the serial i/o2 control register (address 0030 16 ) is set to ??(clock synchronous serial i/o is selected). when bit 6 of the serial i/o2 control register is ??(clock asynchronous serial i/o is selected), the rating values are divide d by 4.
7542 group rev.3.03 jul 11, 2008 page 104 of 117 rej03b0006-0303 switching characteristics t able 25 switching characteristics (1) ( flash rom version: v cc = 4.0 to 5.5v, mask rom version: v cc = 4.0 to 5.5 v , v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 min. t yp. max. symbol parameter limits unit t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ?xd 1 ) t v (s clk1 ?xd 1 ) t r (s clk1 ) t f (s clk1 ) t r (cmos) t f (cmos) serial i/o1, serial i/o2 clock output ??pulse width serial i/o1, serial i/o2 clock output ??pulse width serial i/o1, serial i/o2 output delay time serial i/o1, serial i/o2 output valid time serial i/o1, serial i/o2 clock output rising time serial i/o1, serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) note 1: pin x out is excluded. t able 26 switching characteristics (2) ( flash rom version: v cc = 2.7 to 5.5v, mask rom version: v cc = 2.4 to 5.5 v, v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. t yp. max. symbol parameter limits unit 350 50 50 50 50 note 1: pin x out is excluded. t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ? x d 1 ) t v (s clk1 ? x d 1 ) t r (s clk1 ) t f (s clk1 ) t r (cmos) t f (cmos) serial i/o1, serial i/o2 clock output ??pulse width serial i/o1, serial i/o2 clock output ??pulse width serial i/o1, serial i/o2 output delay time serial i/o1, serial i/o2 output valid time serial i/o1, serial i/o2 clock output rising time serial i/o1, serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 20 20 ns ns ns ns ns ns ns ns 10 10 140 30 30 30 30 ns ns ns ns ns ns ns ns t able 27 switching characteristics (3) ( v cc = 2.2 to 5.5 v , v ss = 0 v, ta = ?0 to 85 ?, unless otherwise noted) min. typ. max. symbol parameter limits unit 450 70 70 70 70 note 1: pin x out is excluded. switching characteristics measurement circuit diagram / / / measured output pin cmos output 100 pf t wh (s clk1 ) t wl (s clk1 ) t d (s clk1 ? x d 1 ) t v (s clk1 ? x d 1 ) t r (s clk1 ) t f (s clk1 ) t r (cmos) t f (cmos) serial i/o1, serial i/o2 clock output ??pulse width serial i/o1, serial i/o2 clock output ??pulse width serial i/o1, serial i/o2 output delay time serial i/o1, serial i/o2 output valid time serial i/o1, serial i/o2 clock output rising time serial i/o1, serial i/o2 clock output falling time cmos output rising time (note 1) cmos output falling time (note 1) t c (s clk1 )/2?0 t c (s clk1 )/2?0 ?0 25 25 ns ns ns ns ns ns ns ns
7542 group rev.3.03 jul 11, 2008 page 105 of 117 rej03b0006-0303 fig. 118 timing chart 0.2v cc t d (s clk1 -txd 1 ) t f 0.2 v cc 0.8v cc 0.8v cc t r t su (rxd 1 -s clk1 )t h (s clk1 -rxd 1 ) t v (s clk1 -txd 1 ) t c (s clk1 ) t wl (s clk1 ) t wh (s clk1 ) r x d 1 (at receive) s clk1 0.2v cc t wl (x in ) 0.8v cc t wh (x in ) t c (x in ) x in 0.2v cc 0.8 v cc t w (reset) reset 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) t c (cntr 0 ) t x d 1 (at transmit) cntr 0 0.2v cc t wl (cntr 0 ) 0.8v cc t wh (cntr 0 ) int 0 , int 1 cap 0 , cap 1
7542 group rev.3.03 jul 11, 2008 page 106 of 117 rej03b0006-0303 package outline 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. y index mark * 3 f 32 25 24 17 16 9 8 1 * 1 * 2 x b p e h e e d h d z d z e detail f l 1 l a c a 2 a 1 previous code jeita package code renesas code plqp0032gb-a 32p6u-a mass[typ.] 0.2g p-lqfp32-7x7-0.80 1.0 0.125 0.35 0.7 0.7 0.20 0.20 0.145 0.09 0.42 0.37 0.32 max nom min dimension in millimeters symbol reference 7.1 7.0 6.9 d 7.1 7.0 6.9 e 1.4 a 2 9.2 9.0 8.8 9.2 9.0 8.8 1.7 a 0.2 0.1 0 0.7 0.5 0.3 l x 8 0 c 0.8 e 0.10 y h d h e a 1 b p b 1 c 1 z d z e l 1 terminal cross section b 1 c 1 bp c y index mark 1 18 19 36 f * 1 * 2 * 3 e h e d e b p a c detail f a 2 l a 1 include trim offset. dimension " * 3" does not note) do not include mold flash. dimensions " * 1" and " * 2" 1. 2. previous code jeita package code renesas code prsp0036ga-a 36p2r-a mass[typ.] 0.5g p-ssop36-8.4x15-0.80 0.2 0.15 0.13 0.5 0.4 0.35 max nom min dimension in millimeters symbol reference 15.2 15.0 14.8 d 8.6 8.4 8.2 e 2.0 a 2 12.23 11.93 11.63 2.4 a 0.05 0.7 0.5 0.3 l 10 0 c 0.8 e 0.15 y h e a 1 b p 0.65 0.95
7542 group rev.3.03 jul 11, 2008 page 107 of 117 rej03b0006-0303 2. 1. dimensions " * 1" and " * 2" do not include mold flash. note) dimension " * 3" does not include trim offset. 16 17 32 1 seating plane * 1 * 2 * 3 * 3 e l a a 1 a 2 d e b 3 b 2 b p c 5.08 a 1 b 3 15 e1.778 c l3.0 0.51 0.9 1.0 1.3 a e8.758 .9 9.05 d27.828. 028.2 reference symbol dimension in millimeters min nom max 0.22 0.27 0.34 p-sdip32-8.9x28-1.78 2.2g mass[typ.] 32p4b prdp0032ba-a renesas code jeita package code previous code b p 0.35 0.45 0.55 10.16 9.86 10.46 b 2 0.63 0.73 1.03 a 2 3.8 0 1.528 2.028 e 1 e 1 previous code jeita package code renesas code pwqn0036ka-a 36pjw-a mass[typ.] 0.07g p-hwqfn36-6x6-0.50 0.7 0.6 0.5 0.25 0.2 0.15 max nom min dimension in millimeters symbol reference 6.1 6.0 5.9 d 6.1 6.0 5.9 e 0.75 a 2 0.8 a 0.05 0 0 4.26 e 1 l p 0.5 e 0.05 x a 1 b p y0.05 d 2 4.26 detail f a 1 a 2 a 9 19 27 1 10 36 18 28 9 19 27 1 10 36 18 28 f x y e d b p l p d 2 e 1 e
7542 group rev.3.03 jul 11, 2008 page 108 of 117 rej03b0006-0303 appendix notes on programming 1. processor status register (1) initializing of processor status register flags which affect program execution must be initialized after a re- set. in particular, it is essential to initialize the t and d flags because they have an important effect on calculations. after a reset, the contents of the processor status register (ps) are undefined except for the i flag which is ?? reset initializing of flags main program fig. 2 stack memory contents after php instruction execution fig. 1 initialization of processor status register (2) how to reference the processor status register to reference the contents of the processor status register (ps), ex- ecute the php instruction once then read the contents of (s+1). if necessary, execute the plp instruction to return the ps to its origi- nal status. (s) (s)+1 stored ps 3. jmp instruction when using the jmp instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. 4.multiplication and division instructions (1) the index x mode (t) and the decimal mode (d) flags do not affect the mul and div instruction. (2) the execution of these instructions does not change the con- tents of the processor status register. set d flag to ? adc or sbc instruction nop instruction sec , clc , or cld instruction fig. 3 status flag at decimal calculations 2. decimal calculations (1) execution of decimal calculations the adc and sbc are the only instructions which will yield proper decimal notation, set the decimal mode flag (d) to ??with the sed instruction. after executing the adc or sbc instruction, ex- ecute another instruction before executing the sec , clc , or cld instruction. (2) notes on status flag in decimal mode when decimal mode is selected, the values of three of the flags in the status register (the n, v, and z flags) are invalid after a adc or sbc instruction is executed. the carry flag (c) is set to ??if a carry is generated as a result of the calculation, or is cleared to ??if a borrow is generated. to de- termine whether a calculation has generated a carry, the c flag must be initialized to ??before each calculation. to check for a borrow, the c flag must be initialized to ??before each calcula- tion.
7542 group rev.3.03 jul 11, 2008 page 109 of 117 rej03b0006-0303 5. read-modify-write instruction do not execute a read-modify-write instruction to the read invalid address (sfr). the read-modify-write instruction operates in the following se- quence: read one-byte of data from memory, modify the data, write the data back to original memory. the following instructions are classified as the read-modify-write instructions in the 740 family. (1) bit management instructions: clb, seb (2) shift and rotate instructions: asl, lsr, rol, ror, rrf (3) add and subtract instructions: dec, inc (4) logical operation instructions (1s complement): com add and subtract/logical operation instructions (adc, sbc, and, eor, and ora) when t flag = ?? operate in the way as the read- modify-write instruction. do not execute the read invalid sfr. when the read-modify-write instruction is executed to read invalid sfr, the instruction may cause the following consequence: the in- struction reads unspecified data from the area due to the read invalid condition. then the instruction modifies this unspecified data and writes the data to the area. the result will be random data written to the area or some unexpected event. notes on peripheral functions notes on i/o ports 1. setting of 32-pin version and pwqn0036ka-a package version (1) set direction registers of ports p2 6 , p2 7 , p3 5 and p3 6 to output. (2) select p3 3 for the int 1 function by the int1 input port selec- tion bit (bit 2 of interrupt edge selection register (address 3a 16 )). (3) be sure to set p3 6 /int 1 input level selection bit (bit 1 of port p1p3 control register (address 17 16 )) to ?? 2. port p0p3 drive capacity control register the number of led drive port (drive capacity is high) is 8. 3. pull-up control register when using each port which built in pull-up resistor as an output port, the pull-up control bit of corresponding port becomes invalid, and pull-up resistor is not connected. pull-up control is effective only when each direction register is set to the input mode. 4. notes in stand-by state in stand-by state* 1 for low-power dissipation, do not make input levels of an input port and an i/o port ?ndefined? pull-up (connect the port to vcc) or pull-down (connect the port to vss) these ports through a resistor. when determining a resistance value, note the following points: ?external circuit ?variation of output levels during the ordinary operation when using a built-in pull-up resistor, note on varied current val- ues: ?when setting as an input port : fix its input level when setting as an output port : prevent current from flowing out to external. the output transistor becomes the off state, which causes the ports to be the high-impedance state. note that the level becomes ?ndefined?depending on external circuits. accordingly, the potential which is input to the input buffer in a mi- crocomputer is unstable in the state that input levels of an input port and an i/o port are ?ndefined? this may cause power source current. * 1 stand-by state : the stop mode by executing the stp instruction the wait mode by executing the wit instruction 5. modifying output data with bit managing instruction when the port latch of an i/o port is modified with the bit manag- ing instruction* 2 , the value of the unspecified bit may be changed. the bit managing instructions are read-modify-write form instruc- tions for reading and writing data by a byte unit. accordingly, when these instructions are executed on a bit of the port latch of an i/o port, the following is executed to all bits of the port latch. ?as for a bit which is set for an input port : the pin state is read in the cpu, and is written to this bit after bit managing. ?as for a bit which is set for an output port : the bit value of the port latch is read in the cpu, and is written to this bit after bit managing. note the following : ?even when a port which is set as an output port is changed for an input port, its port latch holds the output data. ?as for a bit of the port latch which is set for an input port, its value may be changed even when not specified with a bit man- aging instruction in case where the pin state differs from its port latch contents. * 2 bit managing instructions : seb , and clb instructions
7542 group rev.3.03 jul 11, 2008 page 110 of 117 rej03b0006-0303 6. direction register the values of the port direction registers cannot be read. that is, it is impossible to use the lda instruction, memory opera- tion instruction when the t flag is ?? addressing mode using direction register values as qualifiers, and bit test instructions such as bbc and bbs . it is also impossible to use bit operation instructions such as clb and seb and read-modify-write instructions of direction registers for calculations such as ror . for setting direction registers, use the ldm instruction, sta in- struction, etc. t ermination of unused pins 1. terminate unused pins perform the following wiring at the shortest possible distance (20 mm or less) from microcomputer pins. (1) i/o ports set the i/o ports for the input mode and connect each pin to v cc or v ss through each resistor of 1 k ? to 10 k ? . the port which can select a built-in pull-up resistor can also use the built-in pull-up re- sistor. when using the i/o ports as the output mode, open them at ??or ?? ?when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the poten- tial at these pins is undefined and the power source current may increase in the input mode. with regard to an effects on the sys- tem, thoroughly perform system evaluation on the user side. ?since the direction register setup may be changed because of a program runaway or noise, set direction registers by program periodically to increase the reliability of program. 2. termination remarks (1) i/o ports setting as input mode [1] do not open in the input mode. ?the power source current may increase depending on the first- stage circuit. ?an effect due to noise may be easily produced as compared with proper termination (1) shown on the above ?. terminate unused pins? [2] do not connect to v cc or v ss directly. if the direction register setup changes for the output mode be- cause of a program runaway or noise, a short circuit may occur. [3] do not connect multiple ports in a lump to v cc or v ss through a resistor. if the direction register setup changes for the output mode be- cause of a program runaway or noise, a short circuit may occur between ports. notes on interrupts 1. change of relevant register settings when not requiring for the interrupt occurrence synchronous with the following case, take the sequence shown in figure 4. ?when switching external interrupt active edge ?when switching interrupt sources of an interrupt vector address where two or more interrupt sources are allocated fig. 4 sequence of changing relevant register when setting the followings, the interrupt request bit of the corre- sponding interrupt may be set to ?? ?when switching external interrupt active edge int 0 interrupt edge selection bit (bit 0 of interrupt edge selection register (address 3a 16 )) int 1 interrupt edge selection bit (bit 1 of interrupt edge selection register) cntr 0 active edge switch bit (bit 2 of timer x mode register (address 2b 16 )) capture 0 interrupt edge selection bit (bits 1 and 0 of capture mode register (address 20 16 )) capture 1 interrupt edge selection bit (bits 3 and 2 of capture mode register) 2. check of interrupt request bit when executing the bbc or bbs instruction to determine an in- terrupt request bit immediately after this bit is set to ?? take the following sequence. if the bbc or bbs instruction is executed immediately after an in- terrupt request bit is cleared to ?? the value of the interrupt request bit before being cleared to ??is read. set the corresponding interrupt enable bit to ??(disabled) . set the interrupt edge selection bit, active edge switch bit, or the interrupt source selection bit. nop (one or more instructions) set the corresponding interrupt request bit to ? (no interrupt request issued). set the corresponding interrupt enable bit to ??(enabled). set the interrupt request bit to ??(no interrupt issued) nop (one or more instructions) execute the bbc or bbs instruction fig. 5 sequence of check of interrupt request bit
7542 group rev.3.03 jul 11, 2008 page 111 of 117 rej03b0006-0303 3. interrupt discrimination bit use an ldm instruction to clear to ??an interrupt discrimination bit. ldm #%0000xxxx, $0b set the following values to ? ?? an interrupt discrimination bit to clear ?? other interrupt discrimination bits ex.) when a key-on wakeup interrupt discrimination bit is cleared; ldm #%00001110 and $0b. 4. interrupt discrimination bit and interrupt request bit for key-on wakeup, uart1 bus collision detection, a/d conver- sion and timer 1 interrupt, even if each interrupt valid bit (interrupt source set register (address 0a 16 )) is set ?: invalid? each inter- rupt discrimination bit (interrupt source discrimination register (address 0b 16 )) is set to ?: interrupt occurs?when corresponding interrupt request occurs. but corresponding interrupt request bit (interrupt request registers 1, 2 (addresses 3c 16 , 3d 16 ) is not affected. notes on timers 1. when n (0 to 255) is written to a timer latch, the frequency divi- sion ratio is 1/(n+1). 2. when a count source of timer x, timer a or timer b is switched, stop a count of the timer. notes on timer x 1. cntr 0 interrupt active edge selection cntr 0 interrupt active edge depends on the cntr 0 active edge switch bit (bit 2 of timer x mode register (address 2b 16 )). when this bit is ?? the cntr 0 interrupt request bit is set to ??at the falling edge of cntr 0 pin input signal. when this bit is ?? the cntr 0 interrupt request bit is set to ??at the rising edge of cntr 0 pin input signal. 2. timer x count source selection the f(x in ) (frequency not divided) can be selected by the timer x count source selection bits (bits 1 and 0 of timer count source set register (address 2a 16 )) only when the ceramic oscillation or the on-chip oscillator is selected. do not select it for the timer x count source at the rc oscillation. 3. pulse output mode set the direction register of port p1 4 , which is also used as cntr 0 pin, to output. when the tx out pin is used, set the direction register of port p0 3 , which is also used as tx out pin, to output. 4. pulse width measurement mode set the direction register of port p1 4 , which is also used as cntr 0 pin, to input. notes on timer a, b 1. setting of timer value when ?: write to only latch?is set to the timer a (b) write control bit, written data to timer register is set to only latch even if timer is stopped or operating. accordingly, in order to set the initial value for timer when it is stopped, set ?: write to latch and timer simul- taneously?to timer a (b) write control bit. 2. read/write of timer a stop timer a to read/write its data in the following state; x in oscillation selected by clock division ratio selection bits (bits 7 and 6 of cpu mode register (address 3b 16 )), and the on-chip os- cillator output is selected as the timer a count source. 3. read/write of timer b stop timer b to read/write its data in the following state; x in oscillation selected by clock division ratio selection bits, the timer a underflow is selected as the timer b count source, and the on-chip oscillator output is selected as the timer a count source.
7542 group rev.3.03 jul 11, 2008 page 112 of 117 rej03b0006-0303 notes on output compare 1. when the selected source timer of each compare channel is stopped, written data to compare register is loaded to the com- pare latch simultaneously. 2. do not write the same data to both of compare latch x0 (x=0, 1, 2, 3) and x1. 3. when setting value of the compare register is larger than timer setting value, compare match signal is not generated. accord- ingly, the output waveform is fixed to ??or ??level. however, when setting value of another compare register is smaller than timer setting value, this compare match signal is generated. accordingly, if the corresponding compare latch y (y=00, 01, 10, 11, 20, 21, 30, 31) interrupt source bit is set to ? (valid), compare match interrupt request occurs. 4. when the compare x trigger enable bit is cleared to ??(dis- abled), the match trigger to the waveform output circuit is disabled. accordingly, the output waveform can be fixed to ? or ??level. however, in this case, the compare match signal is generated. accordingly, if the corresponding compare latch y (y=00, 01, 10, 1 1, 20, 21, 30, 31) interrupt source bit is set to ? (valid),compare match interrupt request occurs. notes on input capture 1. if the capture trigger is input while the capture register (low-or- der and high-order) is in read, captured value is changed between high-order reading and low-order reading. accordingly, some countermeasure by software is recommended, for ex- ample comparing the values that twice of read. 2. timer a cannot be used for the capture source timer in the fol- lowing state; ?x in oscillation selected by clock division ratio selection bits (bits 7 and 6 of cpu mode register (address 3b 16 )) ?timer a count source: on-chip oscillator output. t imer b cannot be used for the capture source timer in the fol- lowing state; ?x in oscillation selected by clock division ratio selection bits ?timer b count source: timer a underflow ?timer a count source: on-chip oscillator output. 3. as shown below, when the capture input is performed to both capture latch 00 and 01 at the same time, the value of capture 0 status bit (bit 4 of capture/compare status register (address 22 16 )) is undefined (same as capture 1). ?when ??is written to capture latch 00 software trigger bit (bit 0 of capture software trigger register (address 13 16 )) and capture latch 01 software trigger bit (bit 1 of capture software trigger reg- ister) at the same time ?when external trigger of capture latch 00 and software trigger of capture latch 01 occur at the same time ?when external trigger of capture latch 01 and software trigger of capture latch 00 occur at the same time 4. when the capture interrupt is used as the interrupt for return from stop mode, set the capture 0 noise filter clock selection bits (bits 5 and 4 of capture mode register (address 20 16 )) to ?0 (filter stop)?(same as capture 1).
7542 group rev.3.03 jul 11, 2008 page 113 of 117 rej03b0006-0303 3. notes common to clock synchronous serial i/o and uart (1) set the serial i/oi (i=1, 2) control register again after the trans- mission and the reception circuits are reset by clearing both the transmit enable bit and the receive enable bit to ?. fig. 6 sequence of setting serial i/oi control register again clear both the transmit enable bit (te) and the receive enable bit (re) to ? set the bits 0 to 3 and bit 6 of the serial i/oi control register set both the transmit enable bit (te) and the receive enable bit (re), or one of them to ? notes on serial i/oi (i=1, 2) 1. clock synchronous serial i/o (1) when the transmit operation is stopped, clear the serial i/oi enable bit and the transmit enable bit to ??(serial i/oi and transmit disabled). since transmission is not stopped and the transmission circuit is not initialized even if only the serial i/oi enable bit is cleared to ? (serial i/oi disabled), the internal transmission is running (in this case, since pins txd i , rxd i , s clki , and s rdyi function as i/o ports, the transmission data is not output). when data is written to the transmit buffer register in this state, data starts to be shifted to the transmit shift register. when the serial i/oi enable bit is set to ??at this time, the data during internally shifting is output to the txd i pin and an operation failure occurs. (2) when the receive operation is stopped, clear the receive en- able bit to ??(receive disabled), or clear the serial i/oi enable bit to ??(serial i/oi disabled). (3) when the transmit/receive operation is stopped, clear both the transmit enable bit and receive enable bit to ??(transmit and receive disabled) simultaneously. (any one of data transmis- sion and reception cannot be stopped.) in the clock synchronous serial i/o mode, the same clock is used for transmission and reception. if any one of transmission and reception is disabled, a bit error oc- curs because transmission and reception cannot be synchronized. in this mode, the clock circuit of the transmission circuit also oper- ates for data reception. accordingly, the transmission circuit does not stop by clearing only the transmit enable bit to ??(transmit disabled). also, the transmission circuit cannot be initialized even if the serial i/oi enable bit is cleared to ??(serial i/oi disabled) (same as (1)). (4) when signals are output from the s rdyi pin on the reception side by using an external clock, set all of the receive enable bit, the s rdyi output enable bit, and the transmit enable bit to ?? (5) when the s rdyi signal input is used, set the using pin to the in- put mode before data is written to the transmit/receive buffer register. 2. uart when the transmit operation is stopped, clear the transmit enable bit to ??(transmit disabled). same as (1) shown on the above ?. clock synchronous serial i/o? when the receive operation is stopped, clear the receive enable bit to ??(receive disabled). when the transmit/receive operation is stopped, clear the transmit enable bit to ??(transmit disabled) and receive enable bit to ? (receive disabled). (2) the transmit shift completion flag changes from ??to ??with a delay of 0.5 to 1.5 shift clocks. when data transmission is controlled with referring to the flag after writing the data to the transmit buffer register, note the delay. (3) when data transmission is executed at the state that an exter- nal clock input is selected as the synchronous clock, set ??to the transmit enable bit while the s clki is ??state. also, write to the transmit buffer register while the s clki is ??state. (4) when the transmit interrupt is used, set as the following se- quence. ? serial i/oi transmit interrupt enable bit is set to ??(disabled). ? serial i/oi transmit enable bit is set to ?? ? serial i/oi transmit interrupt request bit is set to ??after 1 or more instructions have been executed. ? serial i/oi transmit interrupt enable bit is set to ??(enabled). when the transmit enable bit is set to ?? the transmit buffer empty flag and transmit shift completion flag are set to ?? accordingly, even if the timing when any of the above flags is set to ??is selected for the transmit interrupt source, interrupt request occurs and the transmit interrupt request bit is set. (5) write to the baud rate generator (brgi) while the transmit/re- ceive operation is stopped. can be set with the ldm instruction at the same time
7542 group rev.3.03 jul 11, 2008 page 114 of 117 rej03b0006-0303 notes on serial i/o1 1. i/o pin function when serial i/o1 is enabled. the pin functions of p1 2 /s clk1 and p1 3 /s rdy1 are switched to as follows according to the setting values of a serial i/o1 mode selec- tion bit (bit 6 of serial i/o1 control register (address 1a 16 )) and a serial i/o1 synchronous clock selection bit (bit 1 of serial i/o1 con- trol register). (1) serial i/o1 mode selection bit ??: clock synchronous type serial i/o is selected. ?setup of a serial i/o1 synchronous clock selection bit ??: p1 2 pin turns into an output pin of a synchronous clock. ??: p1 2 pin turns into an input pin of a synchronous clock. ?setup of a s rdy1 output enable bit (srdy) ??: p1 3 pin can be used as a normal i/o pin. ??: p1 3 pin turns into a s rdy1 output pin. (2) serial i/o1 mode selection bit ??: clock asynchronous (uart) type serial i/o is selected. ?setup of a serial i/o1 synchronous clock selection bit ?? p1 2 pin can be used as a normal i/o pin. ?? p1 2 pin turns into an input pin of an external clock. ?when clock asynchronous (uart) type serial i/o is selected, it functions p1 3 pin. it can be used as a normal i/o pin. note on bus collision detection when serial i/o1 is operating at half-duplex communication, set bus collision detection interrupt to be disabled. notes on serial i/o2 1. i/o pin function when serial i/o2 is enabled the pin functions of p0 6 /s clk2 and p0 7 /s rdy2 are switched to as follows according to the setting values of a serial i/o2 mode selec- tion bit (bit 6 of serial i/o2 control register (address 30 16 )) and a serial i/o2 synchronous clock selection bit (bit 2 of serial i/o2 con- trol register). (1) serial i/o2 mode selection bit ??: clock synchronous type serial i/o is selected. ?setup of a serial i/o2 synchronous clock selection bit ??: p0 6 pin turns into an output pin of a synchronous clock. ??: p0 6 pin turns into an input pin of a synchronous clock. ?setup of a s rdy2 output enable bit (srdy) ??: p0 7 pin can be used as a normal i/o pin. ??: p0 7 pin turns into a s rdy2 output pin. (2) serial i/o2 mode selection bit ??: clock asynchronous (uart) type serial i/o is selected. ?setup of a serial i/o2 synchronous clock selection bit ?? p0 6 pin can be used as a normal i/o pin. ?? p0 6 pin turns into an input pin of an external clock. ?when clock asynchronous (uart) type serial i/o is selected, it functions p0 7 pin. it can be used as a normal i/o pin.
7542 group rev.3.03 jul 11, 2008 page 115 of 117 rej03b0006-0303 6. a/d conversion accuracy as for ad translation accuracy, on the following operating condi- tions, accuracy may become low. (1) since the analog circuit inside a microcomputer becomes sen- sitive to noise when v ref voltage is set up lower than vcc voltage, accuracy may become low rather than the case where v ref voltage and vcc voltage are set up to the same value.. (2) when v ref voltage is lower than [ 3.0 v ], the accuracy at the low temperature may become extremely low compared with that at room temperature. when the system would be used at low temperature, the use at v ref =3.0 v or more is recom- mended. notes on watchdog timer 1. the watchdog timer is operating during the wait mode. write data to the watchdog timer control register to prevent timer un- derflow. 2. the watchdog timer stops during the stop mode. however, the watchdog timer is running during the oscillation stabilizing time after the stp instruction is released. in order to avoid the un- derflow of the watchdog timer, the watchdog timer control register must be written just before executing the stp instruc- tion. 3. the stp instruction function selection bit (bit 6 of watchdog timer control register (address 0039 16 )) can be rewritten only once after releasing reset. after rewriting it is disable to write any data to this bit. 4. a count source of watchdog timer is affected by the clock divi- sion selection bit of the cpu mode register. the f(x in ) clock is supplied to the watchdog timer when select- ing f(x in ) as the cpu clock. the on-chip oscillator output is supplied to the watchdog timer when selecting the on-chip oscillator output as the cpu clock. notes on reset pin 1. connecting capacitor in case where the reset signal rise time is long, connect a ce- ramic capacitor or others across the reset pin and the vss pin. and use a 1000 pf or more capacitor for high frequency use. when connecting the capacitor, note the following : ?make the length of the wiring which is connected to a capacitor as short as possible. ?be sure to verify the operation of application products on the user side. if the several nanosecond or several ten nanosecond impulse noise enters the reset pin, it may cause a microcomputer fail- ure. notes on a/d conversion 1. analog input pin make the signal source impedance for analog input low, or equip an analog input pin with an external capacitor of 0.01 f to 1 f. further, be sure to verify the operation of application products on the user side. an analog input pin includes the capacitor for analog voltage com- parison. accordingly, when signals from signal source with high impedance are input to an analog input pin, charge and discharge noise generates. this may cause the a/d conversion/comparison precision to be worse. 2. clock frequency during a/d conversion the comparator consists of a capacity coupling, and a charge of the capacity will be lost if the clock frequency is too low. this may cause the a/d conversion precision to be worse. accordingly, set f(x in ) in order that the a/d conversion clock is 250 khz or over during a/d conversion. 3. a/d conversion clock selection select f(x in )/2 as an a/d conversion clock by setting the a/d con- version clock selection bit (bit 3 of a/d control register (address 34 16 )) when rc oscillation is used. the f(x in ) can be also used as an a/d conversion clock only when ceramic oscillation or on-chip oscillator is used. 4. analog input pin selection p2 6 /an 6 and p2 7 /an 7 can be used only for prsp0036ga-a pack- age version. 5. read a/d conversion register ?8-bit read read only the a/d conversion low-order register (address 35 16 ). ?0-bit read read the a/d conversion high-ordrer register (address 36 16 ) first, and then, read the a/d conversion low-order register (address 35 16 ). in this case, the high-order 6 bits of address 36 16 returns ? when read.
7542 group rev.3.03 jul 11, 2008 page 116 of 117 rej03b0006-0303 notes on clock generating circuit 1. switch of ceramic and rc oscillations after releasing reset, the oscillation mode selection bit (bit 5 of cpu mode register (address 3b 16 )) is ??(ceramic oscillation se- lected). when the rc oscillation is used, after releasing reset, set this bit to ?? 2. double-speed mode the double-speed mode can be used only when a ceramic oscilla- tion is selected. do not use it when an rc oscillation is selected. 3. cpu mode register oscillation mode selection bit (bit 5), processor mode bits (bits 1 and 0) of cpu mode register (address 3b 16 ) are used to select os- cillation mode and to control operation modes of the microcomputer. in order to prevent the dead-lock by erroneously writing (ex. program run-away), these bits can be rewritten only once after releasing reset. after rewriting, it is disabled to write any data to the bit. (the emulator mcu ?37542rss?is excluded.) also, when the read-modify-write instructions (seb, clb, etc.) are executed to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked. 4. clock division ratio, x in oscillation control, on-chip oscillator control the state transition shown in fig. 84 can be performed by setting the clock division ratio selection bits (bits 7 and 6), x in oscillation control bit (bit 4), on-chip oscillator oscillation control bit (bit 3) of cpu mode register. be careful of notes on use in fig. 84. 5. on-chip oscillator operation when the mcu operates by the on-chip oscillator for the main clock, connect x in pin to v cc through a 1 k ? to 10 k ? resistor and leave x out pin open. the clock frequency of the on-chip oscillator depends on the sup- ply voltage and the operation temperature range. be careful that this margin of frequencies when designing applica- tion products. 6. ceramic resonator when the ceramic resonator is used for the main clock, connect the ceramic resonator and the external circuit to pins x in and x out at the shortest distance. externally connect a damping resis- tor rd depending on the oscillation frequency. a feedback resistor is built-in. use the resonator manufacturers recommended value because constants such as capacitance depend on the resonator. 7. rc oscillation when the rc oscillation is used for the main clock, connect the x in pin and x out pin to the external circuit of resistor r and the capacitor c at the shortest distance. the frequency is affected by a capacitor, a resistor and a micro- computer. so, set the constants within the range of the frequency limits. 8. external clock when the external signal clock is used for the main clock, connect the x in pin to the clock source and leave x out pin open. select ??(ceramic oscillation) to oscillation mode selection bit. 9. count source (timer 1, timer a, timer b, timer x, serial i/o, serial i/o2, a/d converter, watchdog timer) a count source of watchdog timer is affected by the clock divi- sion selection bit of the cpu mode register. the f(x in ) clock is supplied to the watchdog timer when select- ing f(x in ) as the cpu clock. the on-chip oscillator output is supplied to the watchdog timer when selecting the on-chip oscillator output as the cpu clock. notes on oscillation control 1. oscillation stop detection circuit (1) when the stop mode is used, set the oscillation stop detection function to ?nvalid? (2) when the ceramic or rc oscillation is stopped by the x in oscil- lation control bit (bit 4 of cpu mode register (address 3b 16 )), set the oscillation stop detection function to ?nvalid? 2. stop mode (1) when the stop mode is used, set the oscillation stop detection function to ?nvalid? (2) when the stop mode is used, set ??( stp instruction enabled) to the stp instruction function selection bit of the watchdog timer control register (bit 6 of watchdog timer control register (address 39 16 )). (3) the oscillation stabilizing time after release of stp instruction can be selected from ?et automatically ??ot set automati- cally?by the oscillation stabilizing time set bit after release of the stp instruction (bit 0 of misrg (address 38 16 )). when ? is set to this bit, ?1 16 ?is set to timer 1 and ?f 16 ?is set to prescaler 1 automatically at the execution of the stp instruc- tion. when ??is set to this bit, set the wait time to timer 1 and prescaler 1 according to the oscillation stabilizing time of the oscillation. also, when timer 1 is used, set values again to timer 1 and prescaler 1 after system is returned from the stop mode. (4) do not execute the stp instruction during the a/d conversion.
7542 group rev.3.03 jul 11, 2008 page 117 of 117 rej03b0006-0303 notes on on-chip oscillation division ratio ? when the clock division ratio is switched from f(x in ) to on-chip oscillator by the clock division ratio selection bits (bits 7 and 6 of cpu mode register (address 3b 16 )), the on-chip oscillator divi- sion ratio (bits 1 and 0 of on-chip oscillation division ratio selection register (address 37 16 )) is ?0 2 ?(on-chip oscillator middle-speed mode (r osc /8)). notes on oscillation stop detection circuit 1. after the reset by the oscillation stop detection, the value of fol- lowing bits are retained, not initialized. ?ceramic or rc oscillation stop detection function active bit bit 1 of misrg (address 3b 16 ) ?oscillation stop detection status bit bit 3 of misrg 2. oscillation stop detection status bit is initialized (?? by the fol- lowing operation. ?external reset ?write ??data to the ceramic or rc oscillation stop detection function active bit. 3. the oscillation stop detection circuit is not included in the emu- lator mcu ?37542rss? notes on cpu rewrite mode t ake the notes described below when rewriting the flash memory in cpu rewrite mode. 1. operation speed during cpu rewrite mode, set the system clock to 4.0 mhz or less using the clock division ratio selection bits (bits 6 and 7 of cpu mode register). 2. instructions inhibited against use the instructions which refer to the internal data of the flash memory cannot be used during cpu rewrite mode. 3. interrupts inhibited against use the interrupts cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. 4. watchdog timer if the watchdog timer has been already activated, internal reset due to an underflow will not occur because the watchdog timer is surely initialized during program or erase. 5. reset reset is always valid. the mcu is activated using the boot mode at release of reset in the condition of cnvss = ?? so that the pro- gram will begin at the address which is stored in addresses fffc 16 and fffd 16 of the boot rom area. electric characteristic differences between mask rom, flash memory mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation among mask rom and flash memory version mcus due to the differences in the manufacturing processes. when manufacturing an application system with the flash memory and then switching to use of the mask rom version, perform suffi- cient evaluations for the commercial samples of the mask rom version. note on power source voltage when the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. notes on hardware handling of power source pin in order to avoid a latch-up occurrence, connect a capacitor suit- able for high frequencies as bypass capacitor between power source pin (vcc pin) and gnd pin (vss pin). besides, connect the capacitor to as close as possible. for bypass capacitor which should not be located too far from the pins to be connected, a ce- ramic capacitor of 0.01 f to 0.1 f is recommended.
revision history rev. date description page summary 7542 group datasheet 1.00 nov 27, 2002 2.00 apr 21, 2003 2.01 dec 03, 2003 2.02 jan 06, 2004 first edition issued features; memory size revised. memory size; flash memory size revised. fig.8; rom size revised. table 2; rom size revised. central processing unit (cpu); description revised. fig.26; port p0 3 direction register revised. fig.42; modulation output revised. fig.43; modulation output revised. reset circuit; description revised. (3) rc oscillation; description revised. (1) oscillation control ?stop mode description about flash added. fig.77; revised. flash memory mode added. electrical characteristics added. features: interrupt, power source voltage, power dissipation revised. fig. 8: development schedule revised. table 2: rom size for flash memory version revised. fig. 12: note added. fig. 14: flash memory control register 2 added. fig. 26: ?pu mode register?added, description for timer 1 interrupt request revised. fig. 29: ?pu mode register?added. fig. 37 and fig. 38: pin name added. fig. 39: pin name added. fig. 46 and fig. 47: pin name added. a-d converter revised. fig. 70 flash memory control register 2 added. fig. 79 (5), (6) revised. a-d converter revised. data required for mask orders revised. description of flash memory control register 0 (bit 2), fig. 83 revised. description of flash memory control register 2, fig. 85 and table 8 added. fig. 86 revised. table 9 revised. electrical characteristics; general purpose revised. extended operating temperature version added. features: the minimum instruction execution time revised. note 2 eliminated. stack pointer (s): reference number of figure in description revised. table 12: p0 7 (busy output) added. fig. 95: ?usy?added to p0 7 . fig. 96, fig. 97: ?usy?added to p0 7 . fig. 98, fig. 99: cnv ss revised. table 19, table 20 timing requirements (general purpose) vcc for flash rom version and mask rom version revised. table 22, table 23 switching characteristics (general purpose) vcc for flash rom version and mask rom version revised. 1 8 9 10 28 36 37 53 55 56 57 65 to 72 73 to 82 1 8 9 13 15 28 30 33 34 40 51 54 59 64 65 68 69 70 71 85 to103 1 10 79 82 83 84 91 93 a - 1
revision history rev. date description page summary 7542 group datasheet 2.03 feb 10, 2004 2.04 apr 14, 2004 2.05 jun 08, 2004 2.06 aug 24, 2004 information about 36pjw-a package version added. - fig.4 pin configuration added. - fig.9 functional block diagram added. - table 1: notes 2, 3 revised. - 36pjw-a package added. - table 2 list of supported products revised. - i/o ports description and fig. 19: note revised. - table 5: notes 2, 3 revised. - intedge revised. - fig.24: note revised. table 12: p0 0 ?0 3 , p0 7 p0 0 ?0 3 fig.100, fig.101: td(cnvss-port) th(cnvss-port) table 17: i cc data for flash rom added. table 18: absolute accuracy for flash rom added. table 29: i cc data for flash rom added. table 30: absolute accuracy for flash rom added. package: description of 36pjw-a revised. table 2: m37542m2-xxxhp added. fig. 79, fig. 80 a bit name revised. countermeasure against noise added. (notes on peripheral functions are included in appendix at the end of this data sheet.) part name revised. 36pjw-a package added. appendix added. features ?programmable i/o ports, ?a/d converter: description added. fig.4: pin 1 to pin 3 revised. m37542f8hp: note added. table 2: m37542f8hp: note added. notes on a/d conversion added. table 7: number of program/erase times revised. fig. 110: figure title and table in figure revised, and note added. m37542f8hp: note added. notes on a/d accuracy added. notes on oscillation stop detection circuit 1: ?each bit of port register pi eliminated. note on power source voltage added. words standardized: on-chip oscillator, a/d converter fig. 97: bits 0 to 3 revised. (1) rom code protect function: some description added. standard serial i/o mode: some description revised. description of standard serial i/o mode 1 and standard serial i/o mode 2 separated. fig. 107 handling example of control pins in standard serial i/o mode 1 added. fig. 112 handling example of control pins in standard serial i/o mode 2 added. 3 8 9 10 11 18 19 23 26 81 86 91 92 101 102 10 11 60 65 to 68 88 108 109 to 118 1 3 11 53 70 88 89 117 119 all pages 73 79 82 83 to 92 86 91 a - 2
revision history rev. date description page summary 7542 group datasheet 3.00 jun 01, 2005 3.01 nov 02, 2005 rom size of flash memory version revised. fig.1 m37542f8gp m37542fxgp fig.2 M37542F8FP m37542fxfp fig.3 m37542f8sp m37542fxsp table 1 performance overview added. table 2 function of vcc, vss revised. flash memory size revised, and fig.10 m37542f4 added. table 3 m37542f4gp,m37542f4fp,m37542f4sp added. fig. 20 (5) port p0 5 revised. table 7 termination of unused pins added. description of serial i/o revised. [uart2 control register (uart2con)] revised. fig. 64 uart2 contorl register revised. description of clock generating circuit revised. fig. 74 revised. fig. 79 revised. table 9 temperature at program/erase added. fig.94 16 kbyte rom product added. table 11 list of software commands (cpu rewrite mode) revised. fig.104 m37542f8gp m37542fxgp fig.105 m37542f8sp m37542fxsp fig.106 M37542F8FP m37542fxfp fig.109 m37542f8gp m37542fxgp fig.110 m37542f8sp m37542fxsp fig.111 M37542F8FP m37542fxfp m37542f4gp,m37542f4fp,m37542f4sp added. table 15 conditions: description added. table 18 note 1 added. table 20, fig. 104 added. table 28 conditions: description added. table 31 note 1 added. table 34, fig. 106 added. extended operating temperature 125 ? version added. (2) how to reference the processor status register revised. fig. 2 revised. package revised. bit name revised: stp instruction disable bit stp instruction function selection bit - description for ?peration of stp instruction function selection bit?revised. - notes on watchdog timer added. - fig.68: blodk diagram of watchdog timer revised. - fig.69: bit 6 and bit 7 of wdtcon revised. bit 6: bit name and its description revised. (bit function is not changed.) stp instruction function selection bit 0 : system enters into the stop mode at the stp instruction execution 1 : internal reset occurs at the stp instruction execution -notes on clock generating circuit : note on count source added. notes on watchdog timer : note on count source added. notes on clock generating circuit : note on count source added. 1 2 3 5 10 11 12 21 24 46 53 54 60 63 72 73 77 86 87 91 92 95 98 100 105 108 110 114-122 125 - - 57 61 132 133 a - 3
revision history rev. date description page summary 7542 group datasheet a - 4 3.02 oct 31, 2006 3.03 jul 11, 2008 table 3 : rom size revised and note 2 added. rom : description added. fig. 15 : note 2 added. table 7 : x in and x out added. notes on watchdog timer : note 3 revised. 5. setup for i/o ports : note eliminated. fig 94 : block diagram revised and note 3 added. 4. brk instruction eliminated. 1. analog input pin : description revised. features: description revised. description, features: ?erial i/o? ?erial interface application: ?ar?deleted. fig. 1, fig. 2 revised. table 1: parameter revised, note 1 deleted. table 2: note 1 deleted. fig. 10 revised. table 3 revised. fig. 20 revised. fig. 21 revised. interrupts revised. ?erial i/o? ?erial interface ?oscillation stop detection circuit: description revised fig. 101: note 2, note 3 revised. fig. 107 revised. fig. 108, fig. 109 revised. fig. 112 revised. fig. 113 revised. electrical characteristics: 1.7542group (general purpose); description revised, ?general purpose)?deleted 2.7542group (extended operating temperature version), 3.7542group (extended operating temperature 125 ? version) deleted. notes on timer a, b: ?bit 0 (bit 2 of timer .... (address 1d 16 ))?deleted. 12 17 24 57, 132 71 73 125 132 1 2 5 10 11 12 21 22 25 to 29 47 66 77 87 88 92 93 96 to 105 111 all trademarks and registered trademarks are the property of their respective owners.
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